Infineon/CYPRESS CY7C1367A-150ACT

The Cypress synchronous burst SRAM family is designed using high-speed, low-power CMOS technology with advanced three-layer polysilicon, dual-layer metal process. Each memory cell consists of four transistors and two high-value resistors. The CY7C1366A/GVT71256C36 and CY7C1367A/GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x 18 SRAM cells, respectively, featuring advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operations. All synchronous inputs are strobed by registers controlled by a positive edge-triggered clock input (CLK). Asynchronous inputs include Output Enable (OE) and burst mode control (MODE). Addresses and chip selects are registered via the Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Addresses, data inputs, and write controls are registered on-chip to initiate a self-timed write cycle. For B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions, four pins are used to implement JTAG test functionality. The CY7C1366A/GVT71256C36 and CY7C1367A/GVT71512C18 operate from a +3.3V supply, with all inputs and outputs compatible with LVTTL.

• Fast access time: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and 150 MHz
• Fast OE access time: 2.5 ns, 3.0 ns, and 3.5 ns
• Performance optimization (two-cycle chip deselect, depth expansion with no wait states)
• 3.3V -5% and +10% power supply
• 3.3V or 2.5V I/O power supply
• 5V-tolerant inputs except I/O
• Clamp diodes on all inputs and outputs to VSS
• Common data input and data output
• Byte write enable and global write control
• Multiple chip selects for depth expansion: three chip selects for TA(GVTI)/A(CY) package versions, two chip selects for B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package versions
• Address pipelining capability
• Address, data, and control registers
• Internal self-timed write cycle
• Burst control pin (interleaved or linear burst sequence)
• Automatic power-down via ZZ mode or CE selection
• JTAG boundary scan support for B/BG and T/AJ package versions
• Thin 119-bump, 14-mm × 22-mm PBGA and 100-pin TQFP packages

• Secondary cache systems
• Pentium and i486 processor systems
• Linear burst sequence processor systems