Infineon/CYPRESS CY7C1399BL-15ZC

The CY7C1399B is a high-performance 3.3V CMOS static random access memory organized as 32768 words × 8 bits. Memory expansion is easily achieved through active-LOW chip enable (CE), output enable (OE), and three-state drivers. The device features an automatic power-down function that reduces power consumption by more than 95% when deselected. The active-LOW write enable (WE) signal controls read and write operations. When both CE and WE inputs are LOW, data on the eight data I/O pins (I/O₀ through I/O₇) is written to the memory location specified by the address on address pins (A₀ through A₁₄). To read the device, it must be selected and the output enabled — CE and OE LOW, with WE inactive (HIGH). Under these conditions, the contents of the location specified by the address pins appear on the eight data I/O pins. The I/O pins remain in a high-impedance state unless the chip is selected, the output is enabled, and WE is HIGH. The CY7C1399B is available in 28-pin standard 300-mil-wide SOJ and TSOP Type I packages.

• Single 3.3V supply
• Ideal for low-voltage cache applications
• High speed — 10/12/15 ns
• Low operating power — 216 mW (max)
• Low-power alpha-particle resistant 6T cell
• Plastic SOJ and TSOP packages

• Low-voltage cache