Infineon/CYPRESS CY7C4221V-15JC

The CY7C42X1V is a high-speed, low-power FIFO memory with a clocked read/write interface, both 9 bits wide. Programmable features include almost-full/almost-empty flags. These FIFOs provide solutions for a wide range of data buffering requirements, including high-speed data acquisition, multiprocessor interfaces, and communications buffering. They feature 9-bit input and output ports, each controlled by independent clock and enable signals. The input port is controlled by a free-running clock (WCLK) and two write enable pins (WEN1, WEN2/LD), while the output port is controlled by a free-running read clock (RCLK), two read enable pins (REN1, REN2), and an output enable pin (OE). The read and write clocks can be tied together for single-clock operation or run independently for asynchronous read/write applications, with clock frequencies up to 66 MHz. Depth expansion is achieved through one enable input for system control and another enable controlled by expansion logic to direct data flow. The family offers four status pins: Empty, Full, Almost Empty, and Almost Full. The almost-empty/almost-full flags are programmable with single-word granularity, with default values of Empty - 7 and Full - 7. All configurations are fabricated using advanced 0.65μm P-well CMOS technology, with input ESD protection greater than 2001V, and latch-up prevention through the use of guard rings.

• High-speed, low-power FIFO memory
• 64 x 9 (CY7C4421V)
• 256 x 9 (CY7C4201V)
• 512 x 9 (CY7C4211V)
• 1K x 9 (CY7C4221V)
• 2K x 9 (CY7C4231V)
• 4K x 9 (CY7C4241V)
• 8K x 9 (CY7C4251V)
• High-speed 66 MHz operation (15 ns read/write cycle time)
• Low power (ICC = 20 mA)
• 3.3V operation for low power and easy integration into low-voltage systems
• 5V-tolerant inputs (VIHmax = 5V)
• Fully asynchronous and simultaneous read/write operation
• Empty, full, programmable almost-empty and almost-full status flags
• TTL compatible
• Output enable (OE) pin
• Separate read and write enable pins
• Center power and ground pins for reduced noise
• Bus-width expansion capability
• Space-saving 32-pin 7mm x 7mm TQFP package
• 32-pin PLCC package
• Available in lead-free packages

• High-speed data acquisition
• Multi-processor interface
• Communication buffering