Infineon/CYPRESS S26KS128SDPBHV020

The HyperFlash family of products are high-speed CMOS, MirrorBit NOR flash devices with the HyperBus low signal count DDR interface, that achieves high speed read throughput. The DDR protocol transfers two data bytes per clock cycle on the data (DQ) signals. A read or write access for the HyperFlash consists of a series of 16-bit wide, one clock cycle data transfers at the internal HyperFlash core and two corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals.

Both data and command/address information are transferred in DDR fashion over the 8-bit data bus. The clock input signals are used for signal capture by the HyperFlash device when receiving command/address/data information on the DQ signals. The Read Data Strobe (RWDS) is an output from the HyperFlash device that indicates when data is being transferred from the memory to the host. RWDS is referenced to the rising and falling edges of CK during the data transfer portion of read operations. Command/address/write-data values are center aligned with the clock edges and read-data values are edge aligned with the transitions of RWDS.

Read and write operations to the HyperFlash device are burst oriented. Read transactions can be specified to use either a wrapped or linear burst. During wrapped operation, accesses start at a selected location and continue for a configured number of locations in a group wrap sequence. During linear operation accesses start at a selected location and continue in a sequential manner until the read operation is terminated, when CS# returns High. Write transactions transfer one or more16-bit values.

• 3.0V I/O, 11 bus signals
• Single ended clock
• 1.8V I/O, 12 bus signals
• Differential clock (CK, CK#)
• Chip Select (CS#)
• 8-bit data bus (DQ[7:0])
• Read-Write Data Strobe (RWDS)
• HyperFlash memories use RWDS only as a Read Data Strobe
• Up to 333 MBps sustained read throughput
• Double-Data Rate (DDR) – two data transfers per clock
• 166-MHz clock rate (333 MBps) at 1.8V VCC
• 100-MHz clock rate (200 MBps) at 3.0V VCC
• 96-ns initial random read access time
• Initial random access read latency: five to 16 clock cycles
• Sequential burst transactions
• Configurable Burst Characteristics
• Wrapped burst lengths: 16 bytes (8 clocks), 32 bytes (16 clocks), 64 bytes (32 clocks)
• Linear burst
• Hybrid option: one wrapped burst followed by linear burst
• Wrapped or linear burst type selected in each transaction
• Configurable output drive strength
• Low Power Modes
• Active Clock Stop During Read: 12 mA, no wake-up require
• Standby: 25 μA (typical), no wake-up required
• Deep Power-Down: 8 μA (typical), 300 μs wake-up required
• INT# output to generate external interrupt
• Busy to Ready Transition
• ECC detection
• RSTO# output to generate system level power-on reset
• User configurable RSTO# Low period
• 512-byte Program Buffer
• Sector Erase
• Uniform 256-KB sectors
• Optional Eight 4-KB Parameter Sectors (32 KB total)
• Advanced Sector Protection
• Volatile and non-volatile protection methods for each sector
• Separate 1024-byte one-time program array
• Operating Temperature
• Industrial (-40℃ to +85℃)
• Industrial Plus (-40℃ to +105℃)
• Extended (-40℃ to +125℃)
• Automotive, AEC-Q100 Grade 3 (-40℃ to +85℃)
• Automotive, AEC-Q100 Grade 2 (-40℃ to +105℃)
• Automotive, AEC-Q100 Grade 1 (-40℃ to +125℃)
• ISO/TS16949 and AEC Q100 Certified
• Endurance
• 100,000 program/erase cycles
• Retention
• 20 year data retention
• Erase and Program Current
• Max Peak ≤100 mA
• Packaging Options
• 24-Ball FBGA
• Additional Features
• ECC 1-bit correction, 2-bit detection
• CRC