Infineon/CYPRESS CY7C1245KV18-400BZXC

CY7C1243KV18 and CY7C1245KV18 are 1.8 V synchronous pipelined SRAMs featuring a QDR II+ architecture. Similar to the QDR II architecture, the QDR II+ architecture consists of two separate ports — a read port and a write port — for accessing the memory array. The read port has dedicated data outputs to support read operations, and the write port has dedicated data inputs to support write operations. The QDR II+ architecture features separate data inputs and data outputs, completely eliminating the data bus turnaround requirement found in common I/O devices. Each port is accessed through a shared address bus. Read and write addresses are latched on alternating rising edges of the input (K) clock. QDR II+ read and write port accesses are completely independent of each other. To maximize data throughput, both read and write ports feature a DDR interface. Each address location is associated with four 18-bit words (CY7C1243KV18) or 36-bit words (CY7C1245KV18), which are sequentially burst into or out of the device. Because data is transferred into and out of the device on every rising edge of the input clocks (K and K), memory bandwidth is maximized while system design is simplified by eliminating bus turnaround. Depth expansion is achieved through port selection, allowing each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the K or K input clocks. Writes are performed through an on-chip synchronous self-timed write circuit.

• Separate read/write data ports
• Concurrent transaction support
• 450 MHz clock for high bandwidth
• Four-word burst for reduced address bus frequency
• DDR interface on read/write ports (data transferred at 900 MHz, clock at 450 MHz)
• 2.0 clock cycle latency available
• Two input clocks (K and K) for precise DDR timing
• SRAM uses rising edge only
• Echo clocks (CQ and CQ) simplify data capture in high-speed systems
• Data valid pin (QVLD) indicates valid data on output
• Single multiplexed address input bus latches address inputs for read/write ports
• Independent port select for depth expansion
• Synchronous internally self-timed writes
• When DOFF is driven HIGH, QDR II+ operates with 2.0-cycle read latency
• When DOFF is driven LOW, operates similar to QDR I devices with 1-cycle read latency
• ×18 and ×36 configurations available
• Full data coherency with latest data provided
• Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
• 1.5 V and 1.8 V I/O supply support
• HSTL inputs and variable drive HSTL output buffers
• 165-ball FBGA package available (13 × 15 × 1.4 mm)
• Lead-free and non-lead-free packages available
• JTAG 1149.1-compatible test access port
• PLL for precise data placement