Infineon/CYPRESS CY7C2570XV18-600BZXC

CY7C2568XV18 and CY7C2570XV18 are 1.8V synchronous pipelined SRAMs featuring a DDR II+ architecture. DDR II+ incorporates an SRAM core with advanced synchronous peripheral circuitry. Read and write addresses are latched on alternating rising edges of the input clock. Write data is registered on the rising edges of K and K. Read data is driven on the rising edges of K and K. Each address location is associated with two 18-bit words or 36-bit words, which are sequentially burst into or out of the device. These devices feature on-chip termination, which helps eliminate external termination resistors, reduce cost, minimize board area, and simplify board routing. Asynchronous inputs include an output impedance matching input. Synchronous data outputs are closely matched to two output echo clocks, eliminating the need to individually capture each SRAM data signal in system designs. All synchronous inputs pass through input registers controlled by the K or K input clock. All data outputs pass through output registers controlled by the K or K input clock. Write operations are performed by an on-chip synchronous self-timed write circuit.

• 72 Mb density
• 633 MHz clock
• Double-word burst to reduce address bus frequency
• Double data rate interface
• 2.5 clock cycle latency available
• Two input clocks for precise double data rate timing
• Echo clock simplifies data capture in high-speed systems
• Data valid pin indicates valid data on output
• On-chip termination feature
• Synchronous internally self-timed write
• Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V
• 1.5 V I/O supply supported
• High-speed transceiver logic inputs and variable drive high-speed transceiver logic output buffers
• 165-ball fine-pitch BGA package available
• JTAG 1149.1-compliant test access port
• PLL for precise data placement