Infineon/CYPRESS CY7C2644KV18-333BZI

CYRS2642KV18 and CYRS2644KV18 are 1.8V synchronous pipelined SRAMs featuring a QDR II+ architecture. Similar to the QDR II architecture, the QDR II+ architecture consists of two separate ports — a read port and a write port — for accessing the memory array. The read port has dedicated data outputs to support read operations, and the write port has dedicated data inputs to support write operations. The QDR II+ architecture features separate data inputs and outputs, completely eliminating the need for data bus "turnaround" found in common I/O devices. Each port is accessed through a shared address bus. Read and write addresses are latched on alternating rising edges of the input (K) clock. Access to the QDR II+ read and write ports is completely independent of each other. To maximize data throughput, both the read and write ports are equipped with DDR interfaces. Each address location is associated with two 18-bit words (CYRS2642KV18) or 36-bit words (CYRS2644KV18), which are sequentially burst in and out of the device. Since data can flow in and out of the device on every rising edge of the two input clocks (K and K#), memory bandwidth is maximized while bus "turnaround" is eliminated, simplifying system design. These devices feature on-die termination (ODT) for D[x:0], BWS[x:0], and K/K# inputs, helping to eliminate external termination resistors, reduce cost, minimize board area, and simplify board routing. Depth expansion is achieved through port selection, allowing each port to operate independently. All synchronous inputs pass through input registers clocked by K or K#, and all data outputs pass through output registers clocked by K or K#. Write operations are performed by an on-chip synchronous self-timed write circuit.

• Non-qualified CYPT2642KV18 and CYPT2644KV18 devices with identical functional and timing characteristics, in 165-ball Ceramic Column Grid Array (CCGA) package
• Separate read/write data ports
• Concurrent transaction support
• 250 MHz clock for high bandwidth
• Two-word burst for reduced address bus frequency
• DDR interface on both read and write ports (data transferred at 500 MHz with 250 MHz clock)
• 2.0 clock cycle latency available
• Two input clocks (K and K̄) for precise DDR timing
• SRAM uses rising edge only
• Echo clocks (CQ and CQ̄) simplify data capture in high-speed systems
• Data valid pin (QVLD) indicates valid data on output
• On-Die Termination (ODT) support
• D[x:0], BWS[x:0], and K/K̄ input support
• Single multiplexed address input bus latches address inputs for read and write ports
• Independent port select for depth expansion
• QDR II+ operates with 2.0-cycle read latency when DOFF is high
• When DOFF is low, operates similarly to QDR I devices with single-cycle read latency
• Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
• 1.5 V and 1.8 V I/O supply support
• High Speed Transceiver Logic (HSTL) inputs and variable-drive HSTL output buffers
• 165-ball CCGA (21 × 25 × 2.83 mm) package
• JTAG 1149.1-compatible test access port
• PLL for precise data placement