Infineon/CYPRESS CY8C3665AXI-016

With its unique array of configurable blocks, PSoC 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip. The CY8C36 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C36 family can handle dozens of data acquisition channels and analog inputs on every general - purpose input/output (GPIO) pin. The CY8C36 family is also a high - performance configurable digital system with some part numbers including interfaces such as USB, multi - master inter - integrated circuit (I²C), and controller area network (CAN). In addition to communication interfaces, the CY8C36 family has an easy to configure logic array, flexible routing to all I/O pins, and current DAC a high - performance single cycle 8051 microprocessor core. You can easily create system - level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator, a hierarchical schematic design entry tool. The CY8C36 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates.

• Single cycle 8051 CPU core DC to 67 MHz operation
• Multiply and divide instructions
• Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, and multiple security features
• Up to 8 - KB flash error correcting code (ECC) or configuration storage
• Up to 8 KB SRAM
• Up to 2 KB electrically erasable programmable read - only memory (EEPROM), 1 M cycles, and 20 years retention
• 24 - channel direct memory access (DMA) with multilayer AHB[1] bus access
• Programmable chained descriptors and priorities
• High bandwidth 32 - bit transfer support
• Low voltage, ultra low - power
• Wide operating voltage range: 0.5 V to 5.5 V
• High efficiency boost regulator from 0.5 - V input through 1.8 - V to 5.0 - V output
• 0.8 mA at 3 MHz, 1.2 mA at 6 MHz, 6.6 mA at 48 MHz
• Low - power modes including:
  • 1 - µA sleep mode with real - time clock (RTC) and low - voltage detect (LVD) interrupt
  • 200 - nA hibernate mode with RAM retention
• Versatile I/O system
• 28 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), two USBIOs[2]
• Any GPIO to any digital or analog peripheral routability
• LCD direct drive from any GPIO, up to 46×16 segments[2]
• CapSense support from any GPIO[3]
• 1.2 - V to 5.5 - V I/O interface voltages, up to four domains
• Maskable, independent interrupt request (IRQ) on any pin or port
• Schmitt - trigger transistor - transistor logic (TTL) inputs
• All GPIO configurable as open drain high/low, pull - up/pull - down, High Z, or strong output
• Configurable GPIO pin state at power - on reset (POR)
• 25 mA sink on SIO
• Digital peripherals
• 20 to 24 programmable logic devices (PLD) based universal digital blocks (UDB)
• Full CAN 2.0b 16 - receive (Rx), 8 - transmit (Tx) buffers[2]
• Full - Speed (FS) USB 2.0 12 Mbps using internal oscillator[2]
• Up to four 16 - bit configurable timer, counter, and PWM blocks

• Consumer applications
• Industrial applications
• Medical applications