RENESAS R7S910018CBG#AC0

300 MHz/450 MHz/600 MHz, MCU with Arm Cortex-R4 and -M3, on-chip FPU, 498/747/996 DMIPS, up to 1 Mbyte of on-chip extended SRAM, Ethernet MAC, EtherCAT, USB 2.0 high-speed, CAN, various communications interfaces such as an SPI multi-I/O bus controller, ΔΣ interface, safety functions, encoder interfaces, and security functions

• On-chip 32-bit Arm Cortex-R4 processor
• High-speed realtime control with maximum operating frequency of 300/450/600 MHz
• Capable of 498/747/996 DMIPS (in operation at 300/450/600 MHz)
• On-chip 32-bit Arm Cortex-R4 (revision r1p4)
• Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes
• Instruction cache/data cache with ECC: 8 Kbytes per cache
• High-speed interrupt
• The FPU supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at singleprecision and double-precision.
• Harvard architecture with 8-stage pipeline
• Supports the memory protection unit (MPU)
• Arm CoreSight architecture, includes support for debugging through JTAG and SWD interfaces
• On-chip 32-bit Arm Cortex-M3 processor (in products incorporating an R-IN engine)
• 150-MHz operating frequency
• On-chip 32-bit Arm Cortex-M3 (revision r2p1)
• RISC Harvard architecture with 3-stage pipeline
• Supports the memory protection unit (MPU)
• Low power consumption
• Standby mode, sleep mode, and module stop function
• On-chip extended SRAM
• Up to 1 Mbyte of the on-chip extended SRAM with ECC 150 MHz
• Data transfer
• DMAC: 16 channels × 2 units
• DMAC for the Ethernet controller: 1 channel
• Event link controller
• Module operations can be started by event signals rather than by interrupt handlers.
• Linked operation of modules is available even while the CPU is in the sleep state.
• Reset and power supply voltage control
• Four reset sources including a pin reset
• Dual power-voltage configuration: 3.3 V (I/O unit), 1.2 V (internal)
• Clock functions
• External clock/oscillator input frequency: 25 MHz
• CPU clock frequency: Up to 300/450/600 MHz
• Low-speed on-chip oscillator (LOCO): 240 kHz
• Independent watchdog timer
• Operated by a clock signal obtained by frequency-dividing the clock signal from the low-speed on-chip oscillator: Up to 120 kHz
• Safety functions
• Register write protection, input clock oscillation stop detection, CRC, IWDTa, and A/D self-diagnosis
• An error control module is incorporated to generate a pin signal output, interrupt, or internal reset in response to errors originating in the various modules.
• Security functions (optional)
• Boot mode with security through encryption
• Encoder interfaces (optional)
• 2 channels
• EnDat 2.2, BiSS-C, FA-CODER, A-format, and HIPERFACE DSL-compliant interfaces
• Frequency-divided output from an encoder
• Various communications interfaces
• Ethernet - EtherCAT slave controller: 2 ports (optional)
• Ethernet MAC: 1 port (an Ethernet switch is not used) or
• Ethernet MAC: 1 port (an Ethernet switch to support 2 ports is used)
• USB 2.0 high-speed host/function : 1 channel
• CAN (compliant with ISO11898-1): 2 channels (max.)
• SCIFA with 16-byte transmission and reception FIFOs: 5 channels
• I²C bus interface: 2 channels for transfer at up to 400 kbps
• RSPIa: 4 channels
• SPIBSC: Provides a single interface for multi-I/O compatible serial flash memory
• External address space
• Buses for high-speed data transfer at 75 MHz (max.)
• Support for up to 6 CS areas
• 8-, 16-, or 32-bit bus space is selectable per area
• 16-bit TPUa (12 channels), MTU3a (9 channels), GPTa (4 channels): Input capture, output compare, PWM waveform output
• 16-bit CMT (6 channels), 32-bit CMTW (2 channels)
• Serial sound interface (1 channel)
• ΔΣ interface
• Up to 4 ΔΣ modulators are connectable externally.
• 12-bit A/D converters
• 12 bits × 2 units (max.) (8 channels for unit 0; 16 channels for unit 1)
• Self diagnosis
• Detection of analog input disconnection
• Temperature sensor for measuring temperature within the chip
• General-purpose I/O ports
• 5-V tolerance, open drain, input pull-up
• Multi-function pin controller
• The locations of input/output functions for peripheral modules are selectable from among multiple pins.