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TI SN74AUC2G08YZPR
| Manufacturer | |
| MPN | SN74AUC2G08YZPR |
| LCSC Part # | C2869204 |
| Packaging | DSBGA-8 |
| Customer # | |
| Key Attributes | 10uA 800mV~2.7V 1.6ns@2.5V,30pF DSBGA-8 Gates and Inverters RoHS |
| Datasheet |  TI SN74AUC2G08YZPR |
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | TI | |
| Packaging | DSBGA-8 | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - High | 1.7V | |
| Logic Family | 74AUC Series | |
| Operating Temperature | -40℃~+85℃ | |
| Input Logic Level - Low | 0V~700mV | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 10uA | |
| Voltage - Supply | 800mV~2.7V | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 9mA | |
| Output Logic Level - Low | - | |
| Propagation Delay | 1.6ns@2.5V,30pF | |
| Current - Output Low(IOL) | 9mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This dual 2-input positive-AND gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation. The SN74AUC2G08 performs the Boolean function A AND B or Y = NOT(NOT(A) OR NOT(B)) in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoFree™ Package
- Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- I_off Supports Partial-Power-Down Mode Operation
- Sub-1-V Operable
- Max propagation delay (tpd) of 1.5 ns at 1.8 V
- Low Power Consumption, 10 μA at 1.8 V
- ±8-mA Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
| Qty | Unit Price | Total Amount |
|---|---|---|
| 1+ | $ 0.4716 | $ 0.47 |
| 10+ | $ 0.4603 | $ 4.60 |
| 30+ | $ 0.4522 | $ 13.57 |
| 100+ | $ 0.444 | $ 44.40 |
Standard Packaging3000/Full Reel | ||
Products Specifications
Show similar products (0) >| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Gates and Inverters | |
| Manufacturer | TI | |
| Packaging | DSBGA-8 | |
| Features | Local shutdown mode;Overvoltage-tolerant input | |
| Input Logic Level - High | 1.7V | |
| Logic Family | 74AUC Series | |
| Operating Temperature | -40℃~+85℃ | |
| Input Logic Level - Low | 0V~700mV | |
| Output Logic Level - High | - | |
| Quiescent Current(Iq) | 10uA | |
| Voltage - Supply | 800mV~2.7V | |
| Number of Channels | 2;2 | |
| Current - Output High(IOH) | 9mA | |
| Output Logic Level - Low | - | |
| Propagation Delay | 1.6ns@2.5V,30pF | |
| Current - Output Low(IOL) | 9mA |
Additional Information
| Type | Details |
|---|---|
| Minimum | 1 |
| Multiple | 1 |
| Standard Packaging | 3000 |
| Sales Unit | Piece |
| EDA Models | EasyEDA Model |
Introduction
This dual 2-input positive-AND gate is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation. The SN74AUC2G08 performs the Boolean function A AND B or Y = NOT(NOT(A) OR NOT(B)) in positive logic. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Features
- Available in the Texas Instruments NanoFree™ Package
- Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- I_off Supports Partial-Power-Down Mode Operation
- Sub-1-V Operable
- Max propagation delay (tpd) of 1.5 ns at 1.8 V
- Low Power Consumption, 10 μA at 1.8 V
- ±8-mA Output Drive at 1.8 V
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |