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TI SN74AUP1G99DCTR product image
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TI SN74AUP1G99DCTR

Manufacturer
TI
MPN
SN74AUP1G99DCTR
LCSC Part #
C2860178
Packaging
MSOP-8
Customer #
Key Attributes
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE WITH 3-STATE OUTPUTS
DatasheetTI SN74AUP1G99DCTR
RoHS Compliance2 documents available
In-Stock: 90
90 In stock, ships now
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QtyUnit PriceTotal Amount
1+$ 0.674$ 0.67
10+$ 0.5467$ 5.47
30+$ 0.4831$ 14.49
100+$ 0.4194$ 41.94
500+$ 0.3819$ 190.95
1,000+$ 0.3623$ 362.30
Standard Packaging3000/Full Reel
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Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Gates and Inverters - Multi-Function, Configurable
ManufacturerTI
PackagingMSOP-8
output typeTri-State
Logic Family74AUP Series
Input typeSchmitt trigger
Propagation Delay7.4ns@3.3V,5pF
Voltage - Supply800mV~3.6V
Operating Temperature-40℃~+85℃
Output Logic Level - Low310mV;440mV
Input Logic Level - High-
Input Logic Level - Low-
Current - Output Low(IOL)4mA
Output Logic Level - High1.03V;1.3V;1.85V;2.55V
Quiescent Current(Iq)900nA
Current - Output High(IOH)4mA
FeaturesLocal shutdown mode;Controllable output enable
Number of Gates1
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Introduction

AI Translation

The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the input-disable feature, which allows floating input signals. The inputs and output are disabled when the output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input. The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and buffer. All inputs can be connected to VCC or GND. This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition and better switching noise immunity at the input. This device is fully specified for partial-power-down applications using l0ff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features

AI Translation
  • Available in the Texas Instruments NanoFree Package
  • Low Static-Power Consumption (ICC = 0.9 μA Max)
  • Low Dynamic-Power Consumption (Cpd = 5 pF Typ at 3.3 V)
  • Low Input Capacitance (CI = 1.5 pF)
  • Low Noise – Overshoot and Undershoot < 10% of Vcc
  • Input-Disable Feature Allows Floating Input Conditions
  • Ioff Supports Partial-Power-Down Mode Operation
  • Includes Schmitt-Trigger Inputs
  • Wide Operating Vcc Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation (tpd = 7.4 ns Max at 3.3 V)
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22 – 2000-V Human-Body Model (A114-B, Class II) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)