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TI CY74FCT2573CTSOCT

Manufacturer
MPN
CY74FCT2573CTSOCT
LCSC Part #
C2675352
Packaging
SOIC-20-300mil
Customer #
Key Attributes
D Latch 4.75V~5.25V 8 1.5ns SOIC-20-300mil Latches RoHS
DatasheetTI CY74FCT2573CTSOCT
RoHS Compliance1 documents available
Alternative Parts5
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Logic/Latches
ManufacturerTI
PackagingSOIC-20-300mil
Quiescent Current0.2mA
Series74FCT
Logic TypeD Latch
Voltage - Supply4.75V~5.25V
Current - Output Low(IOL)12mA
Operating Temperature-40℃~+85℃
Output TypeTri-State
Number of Gates8
Setup Time2ns
Current - Output High(IOH)15mA
Hold Time1.5ns
Propagation Delay1.5ns

Introduction

AI Translation

The CY74FCT2573T is an 8-bit, high-speed CMOS, TTL-compatible octal transparent latch with 3-state outputs, ideally suited for driving high-capacitance loads such as memory and address buffers. The integrated 25 Ω termination resistors at the outputs reduce system noise caused by reflections. When the latch enable (LE) input is HIGH, the flip-flops are transparent to data. When LE transitions from HIGH to LOW, data meeting setup time requirements is latched. When the output enable (OE) input is LOW, data appears on the bus. When OE is HIGH, the bus outputs are in a high-impedance state; data can still be written to the latch in this mode. The device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing destructive backflow current when the device is powered down.

Features

AI Translation
  • Function and pin assignment compatible with the fastest bipolar logic
  • Built-in 25 Ω series resistors on outputs to reduce transmission line reflection noise
  • Low VOH version of equivalent FCT function, with typical VOH of 3.3 V
  • Edge rate control circuitry for significantly improved noise characteristics
  • Ioff supports partial power-down mode operation
  • Matched rise and fall times
  • Three-state outputs
  • ESD protection exceeding JESD 22 standard
  • Meets 2000-V Human Body Model (A114-A)
  • Meets 200-V Machine Model (A115-A)
  • Meets 1000-V Charged Device Model (C101)
  • Fully compatible with TTL input and output logic levels
  • 12 mA sink current, 15 mA source current

Applications

AI Translation
  • Memory buffer
  • Address buffer