TI TPIC6259DWR

This power logic 8-bit addressable latch controls open-drain DMOS transistor outputs and is designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and decoders or demultiplexers. This is a multifunctional device capable of storing single-line data in eight addressable latches with 3-to-8 decoding or demultiplexing mode active-low DMOS outputs. Four distinct modes of operation are selectable by controlling the clear (CLR) and enable overline{G} inputs as enumerated in the function table. In the addressable-latch mode, data at the data-in (D) terminal is written into the addressed latch. The addressed DMOS transistor output inverts the data input with all unaddressed DMOS-transistor outputs remaining in their previous states. In the memory mode, all DMOS-transistor outputs remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latch, enable overline{G} should be held high (inactive) while the address lines are changing. In the 3-to-8 decoding or demultiplexing mode, the addressed output is inverted with respect to the D input and all other outputs are high. In the clear mode, all outputs are high and unaffected by the address and data inputs. Separate power and logic level ground pins are provided to facilitate maximum system flexibility. Pins 1, 10, 11, and 20 are internally connected, and each pin must be externally connected to the power system ground in order to minimize parasitic inductance. A single-point connection between pin 9, logic ground (LGND), and pins 1, 10, 11, and 20, power ground (PGND) must be externally made in a manner that reduces crosstalk between the logic and load circuits. The TPIC6259 is characterized for operation over the operating case temperature range of -40℃ to 125℃.

• Typical on-resistance 1.3Ω, single-pulse avalanche energy 75mJ
• 8 power DMOS transistor outputs; single output supports 250mA continuous current and 1.5A pulsed current
• Output clamp voltage 45V
• Four different operating modes
• Low power consumption
• Pins 1, 10, 11, and 20 are internally connected; each pin requires external connection to power system ground to minimize parasitic inductance; logic ground pin requires a single-point external connection to power ground to reduce crosstalk between logic and load circuits
• Operating case temperature range: -40℃ to 125℃
• Logic supply voltage up to 7V
• Logic input voltage range: -0.3V to 7V
• Power DMOS drain-to-source voltage up to 45V
• Continuous source-drain diode anode current 1A; pulsed source-drain diode anode current 2A
• Operating virtual junction temperature range: -40℃ to 150℃
• Storage temperature range: -65℃ to 150℃

general-purpose storage applications in digital systems; working registers; serial-holding registers; decoders or demultiplexers