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TI DS90LV019TMX/NOPB
| Manufacturer | |
| MPN | DS90LV019TMX/NOPB |
| LCSC Part # | C2671167 |
| Packaging | SOIC-14 |
| Customer # | |
| Key Attributes | DS90LV019 3.3V or 5V LVDS Driver/Receiver |
| Datasheet | TI DS90LV019TMX/NOPB |
| RoHS Compliance | 2 documents available |
| Alternative Parts | 5 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | SOIC-14 | |
| Type | Transceiver | |
| Voltage - Supply | 3.3V;5V | |
| Data Rate | 100Mbps | |
| Operating Temperature | -40℃~+85℃ | |
| Number of Drivers | 1 | |
| Features | Fail-safe;Hot-plug / power-up glitch-free | |
| Level Standard | LVDS | |
| Number of Receivers | 1 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | SOIC-14 | |
| Type | Transceiver | |
| Voltage - Supply | 3.3V;5V | |
| Data Rate | 100Mbps |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Number of Drivers | 1 | |
| Features | Fail-safe;Hot-plug / power-up glitch-free | |
| Level Standard | LVDS | |
| Number of Receivers | 1 |
Introduction
The DS90LV019 is a Driver/Receiver designed specifically for the high speed low power point- to- point interconnect applications. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. The DS90LV019 features an independent driver and receiver with TTL/CMOS compatibility (DIN and ROUT). The logic interface provides maximum flexibility as 4 separate lines are provided (DIN,DE, RE, and ROUT). The device also features a flow- through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver has 3.5mA output loop current. The driver translates between TTL levels (single- ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common- mode noise rejection. The receiver threshold is ±100mV over a ±1V commonmode range and translates the low swing differential levels to standard (TTL/CMOS) levels.
Features
- LVDS Signaling
- 3.3V or 5.0V operation
- Low power CMOS design
- Balanced Output Impedance
- Glitch free power up/down (Driver disabled)
- High Signaling Rate Capacity (above 100 Mbps)
- Ultra Low Power Dissipation
- ±1V Common- Mode Range
- ±100mV Receiver Sensitivity
- Product offered in SOIC and TSSOP packages
- Flow- Through Pin Out
- Industrial Temperature Range Operation
Applications
- High-speed, low-power point-to-point interconnect transmission applications
- LVDS circuit design recommendation: Use at least a 4-layer PCB with dedicated layers for LVDS signals, ground, power, and TTL signals
- LVDS circuit design recommendation: Place drivers and receivers as close as possible to the LVDS port-side connectors
- LVDS circuit design recommendation: Each device requires bypass capacitors combined with distributed bulk capacitors; recommended to place 0.1μF and 0.01μF multilayer ceramic SMT capacitors in parallel between each power pin and ground, positioned as close to the power pins as possible
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | SOIC-14 | |
| Type | Transceiver | |
| Voltage - Supply | 3.3V;5V | |
| Data Rate | 100Mbps | |
| Operating Temperature | -40℃~+85℃ | |
| Number of Drivers | 1 | |
| Features | Fail-safe;Hot-plug / power-up glitch-free | |
| Level Standard | LVDS | |
| Number of Receivers | 1 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Interface/Drivers, Receivers, Transceivers | |
| Manufacturer | TI | |
| Packaging | SOIC-14 | |
| Type | Transceiver | |
| Voltage - Supply | 3.3V;5V | |
| Data Rate | 100Mbps |
| Type | Description | |
|---|---|---|
| Operating Temperature | -40℃~+85℃ | |
| Number of Drivers | 1 | |
| Features | Fail-safe;Hot-plug / power-up glitch-free | |
| Level Standard | LVDS | |
| Number of Receivers | 1 |
Introduction
The DS90LV019 is a Driver/Receiver designed specifically for the high speed low power point- to- point interconnect applications. The device operates from a single 3.3V or 5.0V power supply and includes one differential line driver and one receiver. The DS90LV019 features an independent driver and receiver with TTL/CMOS compatibility (DIN and ROUT). The logic interface provides maximum flexibility as 4 separate lines are provided (DIN,DE, RE, and ROUT). The device also features a flow- through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver has 3.5mA output loop current. The driver translates between TTL levels (single- ended) to Low Voltage Differential Signaling levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common- mode noise rejection. The receiver threshold is ±100mV over a ±1V commonmode range and translates the low swing differential levels to standard (TTL/CMOS) levels.
Features
- LVDS Signaling
- 3.3V or 5.0V operation
- Low power CMOS design
- Balanced Output Impedance
- Glitch free power up/down (Driver disabled)
- High Signaling Rate Capacity (above 100 Mbps)
- Ultra Low Power Dissipation
- ±1V Common- Mode Range
- ±100mV Receiver Sensitivity
- Product offered in SOIC and TSSOP packages
- Flow- Through Pin Out
- Industrial Temperature Range Operation
Applications
- High-speed, low-power point-to-point interconnect transmission applications
- LVDS circuit design recommendation: Use at least a 4-layer PCB with dedicated layers for LVDS signals, ground, power, and TTL signals
- LVDS circuit design recommendation: Place drivers and receivers as close as possible to the LVDS port-side connectors
- LVDS circuit design recommendation: Each device requires bypass capacitors combined with distributed bulk capacitors; recommended to place 0.1μF and 0.01μF multilayer ceramic SMT capacitors in parallel between each power pin and ground, positioned as close to the power pins as possible
C2671167 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 5A991B1 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 5A991B1 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |