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MAXIM MAX11261ENX+T

Manufacturer
MPN
MAX11261ENX+T
LCSC Part #
C2670516
Packaging
WLP-36(2.8x2.8)
Customer #
Key Attributes
24-Bit, 6-Channel, 16ksps, 6.2nV/√Hz PGA, Delta-Sigma ADC with I2C Interface
DatasheetMAXIM MAX11261ENX+T
RoHS Compliance2 documents available
Alternative Parts1
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerMAXIM
PackagingWLP-36(2.8x2.8)
Operating Temperature-40℃~+85℃
InterfaceI2C
Quiescent Current (Iq)1uA
Voltage - Supply2.7V~3.6V
Number of Channels6
Integral non - linearity-
Voltage ReferenceExternal
Clock/OscillatorBuilt-in
Clock Frequency8.192MHz
FeaturesBipolar input;Multi-chip synchronization;Multiplexers;FIFO buffer;Auto calibration
Resolution(Bits)16kHz;24
S/N Ratio-
DNL (LSB)-
ADC architectureSigma-Delta
Programmable GainSupport

Introduction

AI Translation

The MAX11261 is a 6-channel, 24-bit delta-sigma ADC that achieves exceptional performance while consuming very low power. Sample rates up to 16ksps allow precision DC measurements. The device also features a 64-entry, on-chip FIFO to offload the host processor. The MAX11261 communicates through an I2C-compatible serial interface and is available in a small, wafer-level package (WLP). The MAX11261 offers a 6.2nV/√Hz noise programmable gain amplifier (PGA) with gain settings from 1x to 128x. The integrated PGA provides isolation of the signal inputs from the switched capacitor sampling network. The PGA also enables the MAX11261 to interface directly with high-impedance sources without compromising the available dynamic range. The MAX11261 operates from a single 2.7V to 3.6V analog supply. The digital supply range is 1.7V to 2.0V (internal LDO off) and 2.0V to 3.6V (internal LDO on) enabling communication with 1.8V, 2.5V, 3V, or 3.3V logic.

Features

AI Translation
  • Analog Supply: 2.7V to 3.6V
  • Digital Supply:
    • Internal LDO Disabled—1.7V to 2.0V
    • Internal LDO Enabled—2.0V to 3.6V
  • 3ppm INL (typ)
  • PGA:
    • Gains of 1, 2, 4, 8, 16, 32, 64, 128
    • Low-Noise Mode, 6.2nV/√Hz Noise
    • Low-Power Mode, 10nV/√Hz Noise
  • Input-Referred Noise: PGA Low-Noise Mode, Gain of 64 at 1ksps Continuous, 0.15μV RMS
  • Fully Differential Signal and Reference Inputs
  • Internal System Clock of 8.192MHz
  • I2C-Compatible Serial Interface Supports Standard, Fast-Mode, and Fast-Mode Plus I2C Specifications
  • 64-Entry, On-Chip FIFO
  • Hardware Interrupt for Input Monitoring and FIFO Usage
  • On-Demand Self and System Gain and Offset Calibration
  • User-Programmable Offset and Gain Registers
  • Two Power-Down Modes (SLEEP and STANDBY)
  • Low Power Dissipation
  • ESD Rating: ±2.5kV (HBM), 750V (CDM)
  • -40℃ to +85℃ Operating Temperature Range
  • 6x6 Bump, 0.4mm Pitch, 2.838mm x 2.838mm x 0.5mm WLP

Applications

AI Translation
  • Wearable Electronics
  • Medical Equipment
  • Weigh Scales
  • Pressure Sensors Battery-Powered Instrumentation