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EDA ModelsEasyEDA
micron MT41K256M16TW-107:P
| Manufacturer | |
| MPN | MT41K256M16TW-107:P |
| LCSC Part # | C253882 |
| Packaging | FBGA-96(8x14) |
| Customer # | |
| Key Attributes | 4Gb:X4,x8,X16 DDR3L SDRAM |
| Datasheet | micron MT41K256M16TW-107:P |
| Alternative Parts | 5 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | FBGA-96(8x14) | |
| Operating Temperature | 0℃~+95℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Write leveling function;Dynamic on-chip termination;ZQ calibration function | |
| Refresh Current | 15mA | |
| Memory Size | 4Gbit | |
| Voltage - Supply | 32mA;1.283V~1.45V | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | FBGA-96(8x14) | |
| Operating Temperature | 0℃~+95℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Write leveling function;Dynamic on-chip termination;ZQ calibration function |
| Type | Description | |
|---|---|---|
| Refresh Current | 15mA | |
| Memory Size | 4Gbit | |
| Voltage - Supply | 32mA;1.283V~1.45V | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
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Introduction
AI Translation
DDR3L SDRAM (1.35V) is a low voltage version of the DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM (Die Rev :E) data sheet specifications when running in 1.5V compatible mode.
Features
AI Translation
- VDD = VDDQ = 1.35V (1.283–1.45V)
- Backward compatible to VDD = VDDQ = 1.5V ± 0.075V – Supports DDR3L devices to be backward compatible in 1.5V applications
- Differential bidirectional data strobe
- 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#)
- 8 internal banks
- Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
- Programmable CAS (READ) latency (CL)
- Programmable posted CAS additive latency (AL)
- Programmable CAS (WRITE) latency (CWL)
- Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
- Selectable BC4 or BL8 on-the-fly (OTF)
- Self refresh mode
- TC of 105℃ – 64ms, 8192-cycle refresh up to 85℃; 32ms, 8192-cycle refresh at >85℃ to 95℃; 16ms, 8192-cycle refresh at >95℃ to 105℃
- Self refresh temperature (SRT)
- Automatic self refresh (ASR)
- Write leveling
- Multipurpose register
- Output driver calibration
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | FBGA-96(8x14) | |
| Operating Temperature | 0℃~+95℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Write leveling function;Dynamic on-chip termination;ZQ calibration function | |
| Refresh Current | 15mA | |
| Memory Size | 4Gbit | |
| Voltage - Supply | 32mA;1.283V~1.45V | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | micron | |
| Packaging | FBGA-96(8x14) | |
| Operating Temperature | 0℃~+95℃ | |
| Features | Auto self-refresh;Auto precharge function;Asynchronous reset function;Data mask function;Write leveling function;Dynamic on-chip termination;ZQ calibration function |
| Type | Description | |
|---|---|---|
| Refresh Current | 15mA | |
| Memory Size | 4Gbit | |
| Voltage - Supply | 32mA;1.283V~1.45V | |
| Clock Frequency | 933MHz | |
| Memory Format | DDR3L SDRAM |
Help & FeedbackShow similar products (0) >
Introduction
AI Translation
DDR3L SDRAM (1.35V) is a low voltage version of the DDR3 (1.5V) SDRAM. Refer to DDR3 (1.5V) SDRAM (Die Rev :E) data sheet specifications when running in 1.5V compatible mode.
Features
AI Translation
- VDD = VDDQ = 1.35V (1.283–1.45V)
- Backward compatible to VDD = VDDQ = 1.5V ± 0.075V – Supports DDR3L devices to be backward compatible in 1.5V applications
- Differential bidirectional data strobe
- 8n-bit prefetch architecture
- Differential clock inputs (CK, CK#)
- 8 internal banks
- Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals
- Programmable CAS (READ) latency (CL)
- Programmable posted CAS additive latency (AL)
- Programmable CAS (WRITE) latency (CWL)
- Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])
- Selectable BC4 or BL8 on-the-fly (OTF)
- Self refresh mode
- TC of 105℃ – 64ms, 8192-cycle refresh up to 85℃; 32ms, 8192-cycle refresh at >85℃ to 95℃; 16ms, 8192-cycle refresh at >95℃ to 105℃
- Self refresh temperature (SRT)
- Automatic self refresh (ASR)
- Write leveling
- Multipurpose register
- Output driver calibration
C253882 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |