GigaDevice Semicon Beijing GD5F2GM7REYIGR

SPI NAND flash is based on an industry-standard NAND flash memory core, providing embedded systems with an ultra-low-cost, high-density non-volatile storage solution. It is an attractive alternative to SPI-NOR and standard parallel NAND flash, featuring advanced characteristics.

• 8 total pins including VCC and GND
• 2Gb density
• Superior write performance and cost-per-bit advantage over SPI-NOR
• Significantly lower cost than parallel NAND

This low pin-count NAND flash adheres to the industry-standard SPI and maintains the same pinout across all densities. The command set is similar to the common SPI-NOR command set, modified to handle NAND-specific functions with new features added. GigaDevice SPI NAND is an easy-to-integrate NAND flash with purpose-designed features to simplify host management:

• User-selectable internal ECC. ECC parity is generated internally during page program operations. When a page is read into the cache register, ECC parity is checked and errors are corrected as needed. Even with internal ECC enabled, 64 bytes of spare area remain available. The device outputs corrected data and returns ECC error status.
• Internal data move (copyback) with internal ECC. The device can easily refresh and manage garbage collection tasks without moving data in and out. This command string is only available for blocks with the same parity attribute.
• Power-on read with internal ECC. Upon power-on, the device automatically reads the first page of the first block into the cache, allowing the host to read data directly from the cache for easy boot. Furthermore, when ECC is enabled, internal ECC guarantees data integrity.

It is programmed and read in page-based operations and erased in block-based operations. Data is transferred page by page between the NAND flash memory array and the data register and cache register. The cache register is closest to the I/O control circuitry and serves as a data buffer for I/O data; the data register is closest to the memory array and serves as a data buffer for NAND flash memory array operations.

• 2Gb SLC NAND Flash
• Page size:
  • Internal ECC enabled (ECC_EN = 1, default): 2048 bytes + 64 bytes
  • Internal ECC disabled (ECC_EN = 0): 2048 bytes + 128 bytes
• Standard, Dual, Quad SPI, DTR:
  • Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#
  • Dual SPI: SCLK, CS#, SIO0, SIO1, WP#, HOLD#
  • Quad SPI: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
  • DTR (Double Transfer Rate) Read: SCLK, CS#, SIO0, SIO1, SIO2, SIO3
• High-speed clock frequency:
  • 3.3V: 133MHz for Standard/Dual/Quad SPI, 104MHz for DTR Quad SPI
  • 1.8V: 104MHz for Standard/Dual/Quad SPI, 80MHz for DTR Quad SPI
• Software/Hardware write protection:
  • Software write protection for all or part of memory
  • Register protection via WP# pin
  • Power-supply lock-down protection
• Single supply voltage:
  • 1.8V full voltage range: 1.7V ~ 2.0V
  • 3.3V full voltage range: 2.7V ~ 3.6V
• Advanced security feature: 20K bytes OTP area
• Program/Erase/Read speed:
  • Page program time: 320μs typical
  • Block erase time: 3ms typical
  • Page read time: 120μs maximum
• Low power consumption:
  • Maximum active current 30mA
  • Maximum standby current 50μA
• Enhanced access performance: 2K bytes cache for fast random read
• Advanced NAND features:
  • Factory good block 0
  • Deep power-down (1.8V only)
• Reliability:
  • P/E cycles with ECC: 80K typical
  • Data retention: 10 years
• Internal ECC: 8-bit per 528 bytes