ST STM32F100CBT7BTR

Low & medium-density value line, advanced ARM®-based 32-bit MCU with 16 to 128 KB Flash, 12 timers, ADC, DAC & 8 comm interfaces

• Core: ARM® 32-bit Cortex®-M3 CPU
• 24 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance
• Single-cycle multiplication and hardware division
• Memories: 16 to 128 Kbytes of Flash memory – 4 to 8 Kbytes of SRAM
• Clock, reset and supply management: 2.0 to 3.6 V application supply and I/Os, POR, PDR and programmable voltage detector (PVD), 4-to-24 MHz crystal oscillator, Internal 8 MHz factory-trimmed RC, Internal 40 kHz RC, PLL for CPU clock, 32 kHz oscillator for RTC with calibration
• Low power: Sleep, Stop and Standby modes, VBAT supply for RTC and backup registers
• Debug mode: Serial wire debug (SWD) and JTAG interfaces
• DMA: 7-channel DMA controller
• Peripherals supported: timers, ADC, SPIs, I²Cs, USARTs and DACs
• 1×12-bit, 1.2 µs A/D converter (up to 16 channels), Conversion range: 0 to 3.6 V, Temperature sensor
• 2×12-bit D/A converters
• Up to 80 fast I/O ports: 37/51/80 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant
• Up to 12 timers: Up to three 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter, 16-bit, 6-channel advanced-control timer: up to 6 channels for PWM output, dead time generation and emergency stop, One 16-bit timer, with 2 IC/OC, 1 OCN/PWM, dead-time generation and emergency stop, Two 16-bit timers, each with IC/OC/OCN/PWM, dead-time generation and emergency stop, 2 watchdog timers (Independent and Window), SysTick timer: 24-bit downcounter, Two 16-bit basic timers to drive the DAC
• Up to 8 communications interfaces: Up to two I²C interfaces (SMBus/PMBus), Up to 3 USARTs (ISO 7816 interface, LIN, IrDA capability, modem control), Up to 2 SPIs (12 Mbit/s), Consumer electronics control (CEC) interface, CRC calculation unit, 96-bit unique ID
• ECOPACK packages