ISSI IS42S32160B-6BLI-TR

ISSI's 512Mb SDRAM employs a pipelined architecture for high-speed data transfer. All input and output signals are referenced to the rising edge of the clock input. The 512Mb SDRAM is organized as 4Meg x 32-bit x 4 banks. It is a high-speed CMOS DRAM designed for memory systems operating at 3.3V VDD and 3.3V VDDQ, containing 536,870,912 bits. Internally configured as a four-bank DRAM with a synchronous interface, each 134,217,728-bit bank is organized as 8,192 rows x 512 columns x 32 bits. The SDRAM includes an auto refresh mode and a power-saving power-down mode. All signals are registered on the positive edge of the clock signal CLK. All inputs and outputs are LVTTL compatible. It supports synchronous burst data transfers at high data rates with automatic column address generation, the ability to interleave between internal banks to hide precharge time, and random column address changes on every clock cycle during burst access. When auto precharge is enabled, a self-timed row precharge is initiated at the end of the burst sequence. Precharging one bank while accessing one of the other three banks hides the precharge cycle, enabling seamless, high-speed, random access operation. Read and write accesses to the SDRAM are burst-oriented, starting from a selected location and continuing for a programmed number of locations in a programmed sequence. A registered ACTIVE command initiates access, followed by a READ or WRITE command. The ACTIVE command, together with registered address bits, selects the bank and row to be accessed (BA0 and BA1 select the bank; A0–A12 select the row). The READ or WRITE command, together with registered address bits, selects the starting column location for the burst access. Programmable READ or WRITE burst lengths include 1, 2, 4, and 8 locations or full page, with a burst terminate option.

• Clock frequency: 166, 143 MHz
• Fully synchronous; all signals referenced to positive clock edge
• Internal memory banks for hidden row access/precharge
• Single supply: 3.3V ± 0.3V, LVTTL interface
• Programmable burst length - (1, 2, 4, 8, full page)
• Programmable burst sequence: sequential/interleaved
• Auto refresh (CBR)
• Self refresh
• 8192 refresh cycles per 16ms (Grade A2) or 64ms (commercial, industrial, Grade A1)
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write operation capability
• Burst termination via burst stop and precharge commands