RENESAS R7FA4E10D2CNE#AA5

The MCU integrates multiple series of software- and pin- compatible Arm-based 32-bit cores that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. The MCU in this series incorporates a high-performance Arm Cortex-M33 core running up to 100 MHz with the following features: Up to 512 KB code flash memory 128 KB SRAM Quad Serial Peripheral Interface (QSPI) USBFS Analog peripherals Security and safety features

• Arm Cortex@M33 Core:
  • Armv8-M architecture with the main extension
  • Maximum operating frequency: 100 MHz
  • Arm Memory Protection Unit (Arm MPU)
  • Protected Memory System Architecture (PMS/4/8)
  • Secure MPU (MPU 1: 8 regions)
  • Non-secure MPU (MPU_NS): 8 regions
  • SysTick timer
  • Embeds two Systick timers: Secure and Non-secure instance
  • Driven by LOCO or system clock
  • CoreSight™ ETM-M33
• Memory:
  • Up to 512-KB code flash memory
  • 8-KB data flash memory (100,000 program/erase (P/E) cycles)
  • 128-KB SRAM
• Connectivity:
  • Serial Communications Interface (SCI) × 4
  • Asynchronous interfaces
  • 8-bit clock synchronous interface
  • Smart card interface
  • Simple IIC
  • Simple SPI
  • Manchester coding (SCI3, SCI4)
  • I2C bus interface (IIC)
  • Serial Peripheral Interface (SPI)
  • Quad Serial Peripheral Interface (QSPI)
  • USB 2.0 Full-Speed Module (USBFS)
  • Control Area Network module (CAN)
• Analog:
  • 12-bit A/D Converter (ADC12)
  • 12-bit D/A Converter (DAC12)
• Timers:
  • General PWM Timer 32-bit (GPT32) × 2
  • General PWM Timer 16-bit (GPT16) × 2
  • Low Power Asynchronous General Purpose Timer (AGT) × 5
• Security and Encryption:
  • Arm® TrustZone®
  • Up to three regions for the code flash
  • Up to two regions for the data flash
  • Up to three regions for the SRAM
  • Individual secure or non-secure security attribution for each peripheral
• System and Power Management:
  • Low power modes
  • Battery backup function (VBATT)
  • Realtime Clock (RTC) with calendar and VBATT support
  • Event Link Controller (ELC)
  • Data Transfer Controller (DTC)
  • DMA Controller (DMAC) × 8
  • Power-on reset
  • Low Voltage Detection (LVD) with voltage settings
  • Watchdog Timer (WDT)
  • Independent Watchdog Timer (IWDT)
• Multiple Clock Sources:
  • Main clock oscillator (MOSC) (8 to 24 MHz)
  • Sub-clock oscillator (SOSC) (32.768 kHz)
  • High-speed on-chip oscillator (HOCO) (16/18/20 MHz)
  • Middle-speed on-chip oscillator (MOCO) (8 MHz)
  • Low-speed on-chip oscillator (LOCO) (32.768 kHz)
  • IWDT-dedicated on-chip oscillator (15 kHz)
  • Clock trim function for HOCO/MOCO/LOCO
  • PLL/PLL2
  • Clock out support
• General-Purpose I/O Ports:
  • 5-V tolerance, open drain, input pull-up, switchable driving ability
  • Operating Voltage - VCC: 2.7 to 3.6 V
• Operating Temperature: Ta = -40°C to +85°C