TI CD4042BEE4

The CD4042B type contains four latch circuits, each gated by a common clock. Each circuit has complementary buffered outputs. The n-channel and p-channel output devices have balanced impedances, and all outputs are electrically identical. Information at the data inputs is transferred to outputs Q and Q̄ during the clock level programmed by the polarity input. When polarity = 0, transfer occurs during clock level 0; when polarity = 1, transfer occurs during clock level 1. The outputs follow the data inputs as long as the clock and polarity levels defined above are present. When the clock transitions (positive transition when polarity = 0, negative transition when polarity = 1), the information present at the inputs during the clock transition is retained at the outputs until the opposite clock transition occurs. The CD4042B type is available in a 16-pin hermetic DIP ceramic package (F3A suffix), 16-pin DIP plastic package (E suffix), 16-pin small-outline package (D, DR, DT, DW, DWR, and NSR suffixes), and 16-pin thin shrink small-outline package (PW and PWR suffixes).

• Clock polarity control
• Q and Q outputs
• Common clock
• Low power TTL compatible
• Standardized symmetrical output characteristics
• 100% tested for quiescent current at 20 V
• Maximum input current of 1 μA at 18 V over full package-temperature range: 100 nA at 18 V and ±25 ℃
• 5-V, 10-V, and 15-V parametric ratings
• Noise margin (over full package temperature range): 1 V at VDD = 5 V, 2 V at VDD = 10 V, 2.5 V at VDD = 15 V
• Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOs Devices"

• Buffer storage
• Latch registers
• General-purpose digital logic