MICROCHIP MEC1727N-B0-I/SZ-CHR0

This product is a keyboard and embedded controller for laptops. Operating voltages are 3.3V and 1.8V, with an operating temperature range of -40°C to 85°C. The chip is designed to remain in the lowest power consumption state during normal operation, supporting all 5 ACPI power states for PC platforms and 2 chip-level sleep modes (light sleep and deep sleep), with low standby current in sleep mode. It features an ARM Cortex-M4F embedded processor with a programmable clock frequency up to 48 MHz, fixed-point processing unit, and a single 4GB address space. Memory components include 416KB code/data SRAM, 128-byte battery-backed SRAM, 4K-bit OTP, ROM, and internal EEPROM. Clock sources include a 96 MHz internal PLL and a 32 kHz clock source. Package options are 144-pin WFBGA and 176-pin WFBGA. Security features include a boot ROM secure bootloader and hardware accelerators. System host interfaces include eSPI, SPI slave and master controllers, among others. Peripheral features include an internal DMA controller, I2C/SMBus controllers, and general-purpose I/O pins.

• Operating Voltages: 3.3 V and 1.8 V
• Operating Temperature Range: -40 ℃ to 85 ℃
• Chip is designed to always operate in Lowest Power state during Normal Operation
• Supports all 5 ACPI Power States for PC platforms
• Supports 2 Chip-level Sleep Modes: Light Sleep and Heavy Sleep
• Low Standby Current in Sleep Modes
• Programmable clock frequency up to 48 MHz
• Fixed point processor
• Single 4GByte Addressing Space
• Nested Vectored Interrupt Controller (NVIC)
• Maskable Interrupt Controller
• Maskable hardware wake up events
• 8 Levels of priority, individually assignable by vector
• EC Interrupt Aggregator expands number of Interrupt sources supported or reduces number of vectors needed
• Complete ARM Standard debug support
• JTAG-Based DAP port, comprised of SWJDP and AHB-AP debugger access functions
• 416KB Code/Data SRAM
• 352KB optimized for code performance
• 64KB optimized for data performance
• 128 Bytes Battery Powered Storage SRAM
• 4K bits OTP
• In circuit programmable
• Contains Boot ROM
• Contains Runtime APIs for built-in functions
• 128KB of ROM space
• Internal EEPROM
• 4Mbit (512KByte) in-chip SPI Serial Flash in specific packages
• SPI Master controller Supports Mode 0 and mode 3 24MHz
• 96 MHz Internal PLL
• 32 kHz Clock Sources
• Internal 32 kHz silicon oscillator
• External 32 kHz crystal (XTAL) source
• External single-ended 32 kHz clock source
• Boot ROM Secure Boot Loader
• Hardware Root of Trust (RoT) using Secure Boot and Immutable code
• Supports 2 Code Images in external SPI Flash (Primary and Fall back image)
• Authenticates SPI Flash image before loading
• Support AES-256 Encrypted SPI Flash images
• Hardware Accelerators:
• Multi purpose AES Crypto Engine:
• Support for 128-bit - 256-bit key length
• Supports Battery Authentication applications
• Digital Signature Algorithm Support
• Support for ECDSA and EC_KCDSA
• Cryptographic Hash Engine
• Support for SHA-1, SHA-256 to SHA-512
• Public Key Crypto Engine
• Hardware support for RSA and Elliptic Curve asymmetric public key algorithms
• RSA keys length of 1024 to 4096 bits
• ECC Prime Field keys up to 571 bits
• ECC Binary Field keys up to 571 bits
• Microcoded support for standard public key algorithms
• OTP for storing Keys and IDs
• Lockable on 32 B boundaries to prevent read access or write access
• True Random Number Generator
• 1 Kbit FIFO
• JTAG Disabled by default
• Enhanced Serial Peripheral Interface (eSPI)
• Intel eSPI Specification compliant
• eSPI Interface Base Spec, Intel Doc. #327432-004, Rev. 1.0.
• eSPI Compatibility Spec, Intel Doc. #562633, Rev. 0.6
• Support for Master Attached Flash Sharing (MAFS)
• Support for Slave Attached Flash Sharing (SAFS)
• Supports all four channels:
• Peripheral Channel
• Virtual Wires Channel
• Out-of-Band (OOB) Tunneled Message Channel
• Run-time Flash Access Channel
• Supports EC Bus Master to Host Memory
• Supports up to 66 MHz maximum operating frequency
• One Serial Peripheral Interface (SPI) Slave
• Quad SPI (half-duplex) or Single wire (full duplex) support
• Mode 0 and Mode3 operation
• Programmable wait time for response delay
• System to EC Message Interface
• Three Embedded Memory Interfaces
• Provides Two Windows to On-Chip SRAM for Host Access
• Two Register Mailbox Command Interface
• Mailbox Registers Interface
• Thirty-two 8-bit registers
• Two Register Mailbox Command Interfaces
• Two Register SMI Source Interfaces
• Six ACPI Embedded Controller Interfaces
• Five EC Interfaces
• One Power Management Interface
• One Serial Peripheral Interface (SPI) Master Controller
• Dual and Quad I/O Support
• Flexible Clock Rates
• Support for 1.8V and 3.3V slave devices
• SPI Burst Capable
• SPI Controller Operates with Internal DMA Controller with CRC Generation
• Mappable to the following ports (only 1 port active at a time)
• 1 shared SPI Interface
• 2 General purpose SPI
• 1 Private SPI Interface
• 1 In-Chip SPI
• Two General purpose Serial Peripheral Interface (SPI) Controllers
• One EC driven Full Duplex Serial Communication Interface
• Flexible Clock Rates
• SPI burst capable
• 8042 Emulated Keyboard Controller
• 8042 Style Host Interface
• Port 92 Legacy A20M Support
• Fast GATEA20 & Fast CPU_RESET
• 18×8 Interrupt Capable Multiplexed Keyboard Scan Matrix
• Optional Push-Pull Drive for Fast Signal Switching
• PECI Interface 3.1
• Support Intel’s low voltage PECI
• Port 80 BIOS Debug Port
• Two Ports, Assignable to Any eSPI IO Address
• 24-bit Timestamp with Adjustable Timebase
• 16-Entry FIFO
• Internal DMA Controller
• Hardware or Firmware Flow Control
• Firmware Initiated Memory-to-Memory transfers
• Hardware CRC-32 Generator on Channel 0
• 16-Hardware DMA Channels support five SMBus Master/Slave Controllers, One Quad SPI Controller and Two General purpose SPI Controllers
• I2C/SMBus Controllers
• 5 I2C/SMBus controllers
• Up to 16 Configurable I2C ports
• Full Crossbar switch allows any port to be connected to any controller
• Supports Promiscuous mode of operation
• Fully Operational on Standby Power
• Multi-Master Capable
• Supports Clock Stretching
• Programmable Bus Speeds
• 1 MHz Capable
• Supports DMA Network Layer
• General Purpose I/O Pins
• Inputs:
• Asynchronous rising and falling edge wakeup detection
• Interrupt High or Low Level
• Outputs:
• Push Pull or Open Drain output
• Programmable power well emulation
• Pull up or pull down resistor control
• Automatically disabling pull-up resistors when output driven low
• Automatically disabling pull-down resistors when output driven high
• Programmable