TI SN74AVC20T245DGGR

The SN74AVC20T245 is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes. The SN74AVC20T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input is used to disable the outputs so that the buses are isolated. The SN74AVC20T245 is designed so that the control (1DIR, 2DIR, etc., and 2OE) inputs are supplied by VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. To ensure the high-impedance state during power up or power down, OC should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

• Control input VIH/VIL levels referenced to VCCA voltage
• VCC isolation feature: if either VCC input is grounded, both ports enter high-impedance state
• Overvoltage-tolerant inputs/outputs supporting mixed-voltage data communication
• Fully configurable dual-rail design; each port operates across full supply voltage range of 1.2V–3.6V
• Ioff function supports partial power-down operation
• Ioff circuitry disables outputs during power-down to prevent destructive backflow current through the device
• I/O ports withstand 4.6V
• Maximum data rates for various translation scenarios: 1.8V–3.3V translation at 380Mbps; below 1.8V–3.3V translation at 260Mbps; translation to 2.5V at 260Mbps; translation to 1.8V at 210Mbps; translation to 1.5V at 120Mbps; translation to 1.2V at 100Mbps
• Latch-up performance exceeds 100mA per JESD 78 Class II
• ESD protection per JESD 22: HBM 8000V, MM 200V, CDM 1000V
• High-impedance state must be maintained during power-up or power-down; output enable pin requires a pull-up resistor to VCC, with minimum resistance determined by the sink current capability of the driver
• Absolute maximum ratings: VCCA and VCCB supply voltage range −0.5V to 4.6V; I/O ports and control input voltage range −0.5V to 4.6V; output voltage in high-impedance or power-down state −0.5V to 4.6V; output voltage in logic high/low state: Port A −0.5V to VCCA+0.5V, Port B −0.5V to VCCB+0.5V; input clamp current −50mA; output clamp current −50mA; continuous output current ±50mA; continuous current through VCCA, VCCB, and GND ±100mA; DGG package thermal resistance 64°C/W; DGV package thermal resistance 48°C/W; GQL/ZQL package thermal resistance 42°C/W; storage temperature range −65°C to 150°C

• Asynchronous data bus communication
• Bidirectional level translation between different low-voltage nodes