MICROCHIP SY100E195JI-TR

The SY10/100E195 are Programmable Delay Chips (PDCs) primarily used for clock deskewing and timing adjustment. They provide variable delay for differential ECL input transitions.

The delay section consists of a series of gate circuits, as shown in the logic diagram. The gate circuits of the first two delay elements are modified so that their delays are 1.25× and 1.5× the basic gate delay (approximately 80ps), respectively. These two elements provide the E195 with approximately 20ps of digitally selectable resolution. The required device delay is selected by seven address inputs D[0:6], which are latched on-chip by a high signal on the Latch Enable (LEN) control. If the LEN signal is low or floating, the latches are transparent.

Since the delay programmability of the E195 is achieved through purely differential ECL gate delays, the device operates at frequencies >1GHz while maintaining output swings exceeding 600mV.

The E195 therefore provides very fine resolution at very high frequencies, fully selectable from digital inputs, enabling highly precise system clock timing.

The eighth latch input D7 is used to cascade multiple PDCs to extend the programmable range. The cascade logic allows full control over multiple PDCs, with each additional PDC requiring only one additional line on the data bus and no external gating.

• Delay range up to 2ns
• Extended 100E VEE range: -4.2V to -5.5V
• ~20ps/digital step resolution
• Bandwidth >1GHz
• On-chip cascade circuitry
• 75KΩ input pull-down resistor
• Fully compatible with Motorola MC10E/100E195
• 28-pin PLCC package

• To extend the programmable range of the E195, an internal cascading circuit is included. This circuit allows multiple E195 devices to be cascaded without any external gating. Additionally, each additional E195 requires only one more address line. Cascading multiple PDCs will naturally result in a larger programmable range; however, this increase comes at the cost of a longer minimum delay.
• Figure 1 shows the interconnection scheme for cascading two E195 devices. As can be seen, this scheme can be easily extended to larger E195 chains. The D7 input of the E195 is the cascade control pin. Using the interconnection scheme in Figure 1, when D7 is asserted, it indicates that a larger programmable range than a single device can provide is required.
• An expanded view of the latch section of the block diagram is shown below. This diagram will simplify the explanation of how the cascading circuit operates. When D7 of Chip #1 above is low, the cascade output will also be low, and the inverted cascade output will be a logic high. In this case, the SET MIN pin of Chip #2 will be asserted, causing all latches in Chip #2 to be reset, setting the device to minimum delay. Since the RESET and SET inputs of the latches have priority, any changes on the A0–A6 address bus will have no effect on the operation of Chip #2.
• On the other hand, both SET MIN and SET MAX of Chip #1 will be asserted, so its delay will be controlled entirely by the A0–A6 address bus. If the required delay exceeds 31.75 gate delays (1111111 on the A0–A6 address bus), D7 will be asserted to indicate that the delay needs to be cascaded to the next chip.