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ISSI IS43DR16320E-25DBL
| Manufacturer | ISSIAsian Brands |
| MPN | IS43DR16320E-25DBL |
| LCSC Part # | C17490400 |
| Packaging | TWBGA-84(8x12.5) |
| Customer # | |
| Key Attributes | 512Mbit 400MHz DDR2 SDRAM TWBGA-84(8x12.5) Memory RoHS |
| Datasheet | ISSI IS43DR16320E-25DBL |
| RoHS Compliance | 1 documents available |
| Alternative Parts | 5 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | ISSI | |
| Packaging | TWBGA-84(8x12.5) | |
| Operating Temperature | 0℃~+85℃ | |
| Features | Built-in phase-locked loop;Dynamic on-chip termination;Data mask function;Auto precharge function | |
| Refresh Current | 7mA | |
| Memory Size | 512Mbit | |
| Voltage - Supply | 90mA;1.7V~1.9V | |
| Clock Frequency | 400MHz | |
| Memory Format | DDR2 SDRAM |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | ISSI | |
| Packaging | TWBGA-84(8x12.5) | |
| Operating Temperature | 0℃~+85℃ | |
| Features | Built-in phase-locked loop;Dynamic on-chip termination;Data mask function;Auto precharge function |
| Type | Description | |
|---|---|---|
| Refresh Current | 7mA | |
| Memory Size | 512Mbit | |
| Voltage - Supply | 90mA;1.7V~1.9V | |
| Clock Frequency | 400MHz | |
| Memory Format | DDR2 SDRAM |
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Introduction
AI Translation
ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
Features
AI Translation
- VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
- JEDEC standard 1.8V I/O (SSTL_18-compatible)
- Double data rate interface: two data transfers per clock cycle
- Differential data strobe (DQS, DQS)
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 4 internal banks for concurrent operation
- Programmable CAS latency (CL) 3, 4, 5, and 6 supported
- Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
- WRITE latency = READ latency - 1 tCK
- Programmable burst lengths: 4 or 8
- Adjustable data-output drive strength, full and reduced strength options
- On-die termination (ODT)
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | ISSI | |
| Packaging | TWBGA-84(8x12.5) | |
| Operating Temperature | 0℃~+85℃ | |
| Features | Built-in phase-locked loop;Dynamic on-chip termination;Data mask function;Auto precharge function | |
| Refresh Current | 7mA | |
| Memory Size | 512Mbit | |
| Voltage - Supply | 90mA;1.7V~1.9V | |
| Clock Frequency | 400MHz | |
| Memory Format | DDR2 SDRAM |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Memory/Memory | |
| Manufacturer | ISSI | |
| Packaging | TWBGA-84(8x12.5) | |
| Operating Temperature | 0℃~+85℃ | |
| Features | Built-in phase-locked loop;Dynamic on-chip termination;Data mask function;Auto precharge function |
| Type | Description | |
|---|---|---|
| Refresh Current | 7mA | |
| Memory Size | 512Mbit | |
| Voltage - Supply | 90mA;1.7V~1.9V | |
| Clock Frequency | 400MHz | |
| Memory Format | DDR2 SDRAM |
Help & FeedbackShow similar products (0) >
Introduction
AI Translation
ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
Features
AI Translation
- VDD = 1.8V ± 0.1V, VDDQ = 1.8V ± 0.1V
- JEDEC standard 1.8V I/O (SSTL_18-compatible)
- Double data rate interface: two data transfers per clock cycle
- Differential data strobe (DQS, DQS)
- 4-bit prefetch architecture
- On chip DLL to align DQ and DQS transitions with CK
- 4 internal banks for concurrent operation
- Programmable CAS latency (CL) 3, 4, 5, and 6 supported
- Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
- WRITE latency = READ latency - 1 tCK
- Programmable burst lengths: 4 or 8
- Adjustable data-output drive strength, full and reduced strength options
- On-die termination (ODT)
C17490400 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |
| Type | Details |
|---|---|
| RoHS | ROHS Compliant |
| ECCN | EAR99 |
| CNHTS | 8542329000 |
| USHTS | 8542320071 |
| TARIC | 8542329000 |
| Type | Details |
|---|---|
| CAHTS | 8542330000 |
| BRHTS | 85423299 |
| INHTS | 85423200 |
| MXHTS | 8542.32.99 |