ISSI IS46LQ16256A-062TBLA1-TR

The IS43/46LQ16256A/AL and IS43/46LQ32128A/AL are 4Gbit CMOS LPDDR4 SDRAM. The device is organized as 1/2 channels per device, and each channel is 8-banks and 16-bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 16N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 16n bits prefetched to achieve very high bandwidth. On-chip temperature sensor whose status can be read from MR4 • 200-ball x16/x32 BGA (10x14.5mm) in Green Package

LPDDR4-SDRAM is a high-speed synchronous DRAM device internally configured with either 1 or 2 channels. Single-channel is comprised of 8-banks with from 1 Gb to 16 Gb per channel density. Dual channel is comprised of 8-banks with from 2 Gb to 32 Gb total die density. LPDDR4 devices use a 2 or 4 clocks architecture on the Command/Address (CA) bus to reduce the number of input pins in the system. The 6-bit CA bus contains command, address, and bank information. Each command uses 1, 2 or 4 clock cycle, during which command information is transferred on the positive edge of the clock. These devices use a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially an 16n prefetch architecture with an interface designed to transfer two data bits per DQ every clock cycle at the I/O pins. A single read or write access for the LPDDR4 SDRAM effectively consists of a single 16n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one half-clock-cycle data transfers at the 1/O pins. Read and write accesses to the LPDDR4 SDRAMs are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activate command, which is then followed by a Read, Write or Mask Write command. The address and BA bits registered coincident with the Activate command are used to select the row and the bank to be accessed. The address bits registered coincident with the Read, Write or Mask Write command are used to select the bank and the starting column location for the burst access. Prior to normal operation, the LPDDR4 SDRAM must be initialized. The following provides detailed information covering device initialization, register definition, command description and device operation.

• Configuration: 256Mb x16x1 channel, 128Mb x 16x2 channels, 8 internal banks per channel
• Low-voltage Core and I/O Power Supplies: VDD1 = 1.70 - 1.95V, VDD2 = 1.06 - 1.17V, VDDQ = 1.06 - 1.17V (LPDDR4), VDDQ = 0.57–0.65V (LPDDR4X)
• LVSTL (Low Voltage Swing Terminated Logic) I/O Interface
• Internal VREF and VREF Training
• Dynamic ODT: DQ ODT: VSSQ Termination, CA ODT: VSS Termination
• Max. Clock Frequency: 1.6GHz (3.2Gbps)
• 16n Pre-fetch DDR architecture
• Single data rate (multiple cycles) command/ address bus
• Bidirectional/differential data strobe per byte of data (DQS/DQS#)
• Programmable burst lengths (16 or 32)
• ZQ Calibration
• Operation Temperature: Industrial (TC = -40℃ to 95℃), Automotive, A1 (TC = -40℃ to 95℃), Automotive, A2 (TC = -40℃ to 105℃), Automotive, A3 (TC = -40℃ to 125℃)
• Clock-Stop capability