Alliance Memory AS4C32M16D1A-5TCN

The 512Mb DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 512 Mbits. It is internally configured as a quad 8M x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CK). Data outputs occur at both rising edges of CK and CK. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The device provides programmable Read or Write burst lengths of 2, 4, or 8. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, 512Mb DDR features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth, result in a device particularly well suited to high performance main memory and graphics applications.

• Fast clock rate: 200MHz
• Differential Clock CK & CK
• Bi-directional DQS
• DLL enable/disable by EMRS
• Fully synchronous operation
• Internal pipeline architecture
• Four internal banks, 8M x 16-bit for each bank
• Programmable Mode and Extended Mode registers
• CAS Latency: 2, 2.5, 3
• Burst length: 2, 4, 8
• Burst Type: Sequential & Interleaved
• Individual byte write mask control
• DM Write Latency = 0
• Auto Refresh and Self Refresh
• 8192 refresh cycles / 64ms
• Precharge & active power down
• Power supplies: VDD & VDDQ = 2.5V ± 0.2V
• Operating Temperature:
  • Commercial (0℃~70℃)
  • Industrial (-40℃~85℃)
• Interface: SSTL_2 I/O Interface
• Package: 66 Pin TSOP II, 0.65mm pin pitch
• Pb and Halogen free