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AMD/XILINX XC95144XL-7CSG144C
| Manufacturer | |
| MPN | XC95144XL-7CSG144C |
| LCSC Part # | C1556128 |
| Packaging | LCSBGA-144 |
| Customer # | |
| Key Attributes | LCSBGA-144 FPGAs (Field Programmable Gate Array) RoHS |
| Datasheet | AMD/XILINX XC95144XL-7CSG144C |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | AMD/XILINX | |
| Packaging | LCSBGA-144 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | AMD/XILINX |
| Type | Description | |
|---|---|---|
| Packaging | LCSBGA-144 |
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Introduction
AI Translation
The XC95144XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns.
Features
AI Translation
- 5 ns pin-to-pin logic delays
- System frequency up to 178 MHz
- 144 macrocells with 3,200 usable gates
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-CSP (117 user I/O pins)
- Pb-free available for all packages
- Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
- Fast FLASH technology
- Advanced system features
- In-system programmable
- Superior pin-locking and routability with Fast CONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin with local inversion
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000V
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 23.8121 | $ 23.81 |
| 200+ | $ 9.2163 | $ 1843.26 |
| 500+ | $ 8.8913 | $ 4445.65 |
| 1,000+ | $ 8.7312 | $ 8731.20 |
Standard Packaging198/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | AMD/XILINX | |
| Packaging | LCSBGA-144 |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/FPGAs (Field Programmable Gate Array) | |
| Manufacturer | AMD/XILINX |
| Type | Description | |
|---|---|---|
| Packaging | LCSBGA-144 |
Help & FeedbackShow similar products (0) >
Introduction
AI Translation
The XC95144XL is a 3.3V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 5 ns.
Features
AI Translation
- 5 ns pin-to-pin logic delays
- System frequency up to 178 MHz
- 144 macrocells with 3,200 usable gates
- 100-pin TQFP (81 user I/O pins)
- 144-pin TQFP (117 user I/O pins)
- 144-CSP (117 user I/O pins)
- Pb-free available for all packages
- Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
- Fast FLASH technology
- Advanced system features
- In-system programmable
- Superior pin-locking and routability with Fast CONNECT II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with individual product-term allocation
- Local clock inversion with three global and one product-term clocks
- Individual output enable per output pin with local inversion
- Input hysteresis on all user and boundary-scan pin inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Excellent quality and reliability
- Endurance exceeding 10,000 program/erase cycles
- 20 year data retention
- ESD protection exceeding 2,000V
C1556128 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |