NXP MPC8315CVRAFDA

The MPC8315E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In addition to the e300 core, the SoC platform includes features such as dual enhanced three-speed 10, 100, 1000 Mbps Ethernet controllers (eTSECs) with SGMII support, a 32- or 16-bit DDR1/DDR2 SDRAM memory controller, dual SATA 3 Gbps controllers (MPC8315E-specific), a security engine to accelerate control and data plane security protocols, and a high degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration. The MPC8315E also offers peripheral interfaces such as a 32-bit PCI interface with up to 66 MHz operation, 16-bit enhanced local bus interface with up to 66 MHz operation, TDM interface, and USB 2.0 with an on-chip USB 2.0 PHY. The MPC8315E offers additional high-speed interconnect support with dual integrated SATA 3 Gbps interfaces and dual single-lane PCI Express interfaces. When not used for PCI Express, the SerDes interface may be configured to support SGMII. The MPC8315E security engine (SEC 3.3) allows CPU-intensive cryptographic operations to be offloaded from the main CPU core.

• e300 Core:
  • Operates at up to 400 MHz
  • 16-Kbyte instruction cache, 16-Kbyte data cache
  • One floating point unit and two integer units
  • Software-compatible with the Freescale processor families implementing the PowerPC Architecture
  • Performance monitor
• Serial Interfaces:
  • Two enhanced TSECs (eTSECs)
  • Two Ethernet interfaces using one RGMII/MII/RMII/RTBI or SGMII (no GMII)
  • Dual UART, one I²C, and one SPI interface
• Security Engine:
  • Optimized to handle all the algorithms associated with IPSec, 802.11i, and iSCSI
  • Contains one crypto-channel, a controller, and a set of crypto execution units (EUs)
  • Public key execution unit (PKEU): RSA and Diffie-Hellman (to 4096 bits), Programmable field size up to 2048 bits, Elliptic curve cryptography (1023 bits), F2m and F(p) modes, Programmable field size up to 511 bits
  • Data encryption standard execution unit (DEU): DES, 3DES, Two key (K1, K2) or three key (K1, K2, K3), ECB, CBC, CFB-64 and OFB-64 modes for both DES and 3DES
  • Advanced encryption standard unit (AESU): Implements the Rinjdael symmetric key cipher, Key lengths of 128, 192, and 256 bits, ECB, CBC, CCM, CTR, GCM, CMAC, OFB, CFB, XCBC-MAC and LRW modes, XOR acceleration
  • Message digest execution unit (MDEU): SHA with 160-bit, 256-bit, 384-bit and 512-bit message digest, SHA-384/512, MD5 with 128-bit message digest, HMAC with either algorithm
  • Random number generator (RNG): Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random Number Generator (PRNG)
  • Cyclical Redundancy Check Hardware Accelerator (CRCA): Implements CRC32C as required for iSCSI header and payload checksums, CRC32 as required for IEEE 802 packets, as well as for programmable 32 bit CRC polynomials
• DDR Memory Controller:
  • Single 16- or 32-bit interface supporting both DDR1 and DDR2 SDRAM
  • Support for up to 266 MHz data rate
  • Support for two physical banks (chip selects), each bank independently addressable
  • 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with x8/x16 data ports (no direct x4 support)
  • Support for one 16-bit device or two 8-bit devices on a 16-bit bus or two 16-bit devices on a 32-bit bus
  • Support for up to 16 simultaneous open pages
  • Supports auto refresh
  • On-the-fly power management using CKE
  • 1.8-/2.5-V SSTL2 compatible I/O

• Storage applications
• Consumer applications
• Industrial applications
• Main CPUs and I/O processors in network attached storage (NAS)
• Voice over IP (VoIP) router/gateway
• Intelligent wireless LAN (WLAN)
• Set top boxes
• Industrial controllers
• Wireless access points