TI AM1705DPTPD4

M1705 is a low-power ARM microprocessor based on an ARM9. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices with robust operating systems, rich user interfaces, and high processor performance through the maximum flexibility of a fully integrated, mixed processor solution. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-, 16-, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core has separate 16KB of instruction and 16-KB data caches. Both memory blocks are 4-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I²C Bus interfaces; three multichannel audio serial ports (McASPs) with serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The I²C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. The device has a complete set of development tools for the ARM processor. These tools include C compilers and a Windows debugger interface for visibility into source code execution.

• 375- and 456-MHz ARM926EJ-S RISC Core – 32-Bit and 16-Bit (Thumb) Instructions – Single-Cycle MAC – ARM Jazelle Technology – Embedded ICE-RT for Real-Time Debug
• ARM9 Memory Architecture – 16KB of Instruction Cache – 16KB of Data Cache – 8KB of RAM (Vector Table) – 64KB of ROM
• Enhanced Direct Memory Access Controller 3 (EDMA3): – 2 Transfer Controllers – 32 Independent DMA Channels – 8 Quick DMA Channels – Programmable Transfer Burst Size
• 128KB of RAM Memory
• 3.3-V LVCMOS I/Os (Except for USB Interface)
• Two External Memory Interfaces: – EMIFA – NOR (8-Bit-Wide Data) – NAND (8-Bit-Wide Data) – EMIFB – 16-Bit SDRAM With 128-MB Address Space
• Three Configurable 16550-Type UART Modules: – UART0 With Modem Control Signals – 16-Byte FIFO – 16x or 13x Oversampling Option – Autoflow Control Signals (CTS, RTS) on UART0 Only
• Two Serial Peripheral Interfaces (SPIs) Each With One Chip Select
• Programmable Real-Time Unit Subsystem (PRUSS) – Two Independent Programmable Real-Time Unit (PRU) Cores – 32-Bit Load-Store RISC Architecture – 4KB of Instruction RAM per Core – 512 Bytes of Data RAM per Core – PRUSS can be Disabled Through Software to Save Power – Standard Power-Management Mechanism – Clock Gating – Entire Subsystem Under a Single PSC Clock Gating Domain – Dedicated Interrupt Controller – Dedicated Switched Central Resource
• Multimedia Card (MMC)/Secure Digital (SD) Card Interface With Secure Data I/O (SDIO)
• Two Master and Slave Inter-Integrated Circuit (I²C Bus)
• USB 2.0 OTG Port With Integrated PHY (USB0) – USB 2.0 Full-Speed Client – USB 2.0 Full- and Low-Speed Host – End Point 0 (Control) – End Points 1, 2, 3, and 4 (Control, Bulk, Interrupt, or ISOC) RX and TX
• Two Multichannel Audio Serial Ports (McASPs): – Six Clock Zones and 28 Serial Data Pins – Supports TDM, I2S, and Similar Formats – FIFO Buffers for Transmit and Receive
• 10/100 Mbps Ethernet MAC (EMAC): – IEEE 802.3 Compliant (3.3-V I/O Only) – RMII Media-Independent Interface – Management Data I/O (MDIO) Module
• One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
• One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
• Three Enhanced Pulse Width Modulators (eHRPWMs): – Dedicated 16-Bit Time-Base Counter With Period and Frequency Control – 6 Single-Edge, 6 Dual-Edge Symmetric, or 3 Dual-Edge Asymmetric Outputs – Dead-Band Generation – PWM Chopping by High-Frequency Carrier – Trip Zone Input
• Three 32-Bit Enhanced Capture (eCAP) Modules: – Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs – Single-Shot Capture of up to Four Event Timestamps
• Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
• 176-Pin PowerPAD Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
• Commercial, Industrial, or Extended Temperature

• Industrial Automation
• Home Automation
• Test and Measurement
• Portable Data Terminals