TI 74ACT11074N
| Manufacturer | |
| MPN | 74ACT11074N |
| LCSC Part # | C1550115 |
| Packaging | PDIP-14 |
| Customer # | |
| Key Attributes | 4.5V~5.5V 1 2 8.5ns@5V,50pF PDIP-14 Flip Flops RoHS |
| Datasheet | TI 74ACT11074N |
| RoHS Compliance | 1 documents available |
| Alternative Parts | 5 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | PDIP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+85℃ | |
| Series | 74ACT Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 4.5ns | |
| Quiescent Current | 4uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.5ns@5V,50pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | PDIP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+85℃ | |
| Series | 74ACT Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 2 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 4.5ns | |
| Quiescent Current | 4uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.5ns@5V,50pF | |
| Trigger Type | Rising Edge |
Introduction
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The 74ACT11074 is characterized for operation from -40℃ to 85℃.
Features
- Inputs Are TTL-Voltage Compatible
- Center-Pin Vcc and GND Configurations to Minimize High-Speed Switching Noise
- EPIC (Enhanced-Performance Implanted CMOS) 1-μm Process
- 500 mA Typical Latch-Up Immunity at 125℃
- Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | PDIP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+85℃ | |
| Series | 74ACT Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 4.5ns | |
| Quiescent Current | 4uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.5ns@5V,50pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | PDIP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+85℃ | |
| Series | 74ACT Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 2 | |
| Current - Output High(IOH) | 24mA | |
| Current - Output Low(IOL) | 24mA | |
| Setup Time | 4.5ns | |
| Quiescent Current | 4uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.5ns@5V,50pF | |
| Trigger Type | Rising Edge |
Introduction
This device contains two independent positive-edge-triggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements are transferred to the outputs on the low-to-high transition of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold time interval, data at the D input may be changed without affecting the levels at the outputs. The 74ACT11074 is characterized for operation from -40℃ to 85℃.
Features
- Inputs Are TTL-Voltage Compatible
- Center-Pin Vcc and GND Configurations to Minimize High-Speed Switching Noise
- EPIC (Enhanced-Performance Implanted CMOS) 1-μm Process
- 500 mA Typical Latch-Up Immunity at 125℃
- Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, and Standard Plastic 300-mil DIPs (N)
C1550115 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |