MAXIM MAX194BCPE+

The MAX194 is a 14-bit successive-approximation analog-to-digital converter (ADC) that combines high speed, high accuracy, low power consumption, and a 10µA shutdown mode. Internal calibration circuitry corrects linearity and offset errors to maintain the full rated performance over the operating temperature range without external adjustments. The capacitive-DAC architecture provides an inherent 85ksps track/hold function. The MAX194, with an external reference (up to +5V), offers a unipolar (0V to VREF) or bipolar (-VREF to VREF) pin-selectable input range. Separate analog and digital supplies minimize digital-noise coupling. The chip select (CS) input controls the three-state serial-data output. The output can be read either during conversion as the bits are determined, or following conversion at up to 5Mbps using the serial clock (SCLK). The end-of-conversion (EOC) output can be used to interrupt a processor, or can be connected directly to the convert input (CON) for continuous, full-speed conversions. The MAX194 is available in 16-pin DIP, wide SO, and ceramic sidebraze packages. The output data format provides pin-for-pin and functional compatibility with the 16-bit MAX195 ADC. The MAX194 uses a successive-approximation register (SAR) to convert an analog input to a 14-bit digital code, which outputs as a serial data stream. The data bits can be read either during the conversion, at the CLK clock rate, or between conversions asynchronous with CLK, at the SCLK rate (up to 5Mbps). The MAX194 includes a capacitive digital-to-analog converter (DAC) that provides an inherent track/hold input. The interface and control logic are designed for easy connection to most microprocessors (µPs), limiting the need for external components. In addition to the SAR and DAC, the MAX194 includes a serial interface, a sampling comparator used by the SAR, ten calibration DACs, and control logic for calibration and conversion. The DAC consists of an array of capacitors with binary weighted values plus one “dummy sub-LSB” capacitor. During input acquisition in unipolar mode, the array’s common terminal is connected to AGND and all free terminals are connected to the input signal (AIN). After acquisition, the common terminal is disconnected from AGND and the free terminals are disconnected from AIN, trapping a charge proportional to the input voltage on the capacitor array. The free terminal of the MSB (largest) capacitor is connected to the reference (REF), which pulls the common terminal (connected to the comparator) pos

• True 14-Bit Accuracy: 1⁄2LSB INL 82dB SINAD
• 9.4µs Conversion Time
• 10µA Shutdown Mode
• Built-In Track/Hold
• AC and DC Specified
• Unipolar (0V to VREF) and Bipolar (-VREF to VREF) Input Range
• Three-State Serial-Data Output
• Small 16-Pin DIP, SO, and Ceramic SB Packages
• Pin-Compatible 16-Bit Upgrade (MAX195)