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TI TLC3548CPW

Manufacturer
MPN
TLC3548CPW
LCSC Part #
C1543080
Packaging
TSSOP-24
Customer #
Key Attributes
SPI 4.5V~5.5V TSSOP-24 Analog to Digital Converters (ADC) RoHS
DatasheetTI TLC3548CPW
RoHS Compliance1 documents available
Alternative Parts3
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC)
ManufacturerTI
PackagingTSSOP-24
Operating Temperature0℃~+70℃
InterfaceSPI
Quiescent Current (Iq)-
Voltage - Supply4.5V~5.5V
Number of Channels8
Integral non - linearity1LSB
Voltage ReferenceBuilt-in
Clock/OscillatorBuilt-in
Clock Frequency6.5MHz
FeaturesMultiplexers;FIFO buffer;Synchronous triggering
Resolution(Bits)200kHz;14
S/N Ratio81dB
DNL (LSB)0.5LSB
ADC architectureSAR
Programmable GainNot supported

Introduction

AI Translation

The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS analog-to-digital converters (ADC). All devices operate from a single 5V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital inputs [chip select (CS), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS, slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual converter. CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power-on, and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS) are needed to interface with the host. In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low power consumption. The power saving feature is further enhanced with software power-down/ autopower-down modes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548 have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-V external reference is used.