MICROCHIP ZL30100QDG1

The ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment. The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable. The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.

• Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E
• Supports ITU-T G.823 and G.824 for 2048 kbit/s and 1544 kbit/s interfaces
• Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces
• Simple hardware control interface
• Accepts two input references and synchronizes to any combination of 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz or 16.384 MHz inputs
• Provides a range of clock outputs: 1.544 MHz, 2.048 MHz, 16.384 MHz and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz
• Hitless reference switching between any combination of valid input reference frequencies
• Provides 5 styles of 8 kHz framing pulses
• Holdover frequency accuracy of 1.5×10⁻⁷
• Lock, Holdover and selectable Out of Range indication
• Selectable loop filter bandwidth of 1.8 Hz or 922 Hz
• Less than 0.6 nsₚₚ intrinsic jitter on all output clocks
• External master clock source: clock oscillator or crystal

• Synchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXs
• Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses
• Line Card synchronization for PDH systems