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RENESAS 9DB633AGLF

Manufacturer
MPN
9DB633AGLF
LCSC Part #
C1540616
Packaging
TSSOP-28
Customer #
Key Attributes
3.3V 6 TSSOP-28 Application Specific Clock/Timing RoHS
DatasheetRENESAS 9DB633AGLF
Every Order Guarantee
100% Authentic · 30-Day Return or Replacement

Products Specifications

All
TypeDescription
CategoryIntegrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing
ManufacturerRENESAS
PackagingTSSOP-28
Voltage - Supply3.3V
FeaturesLow-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown
Output Frequency(Max)-
Operating Temperature0℃~+70℃
Number of outputs6

Introduction

AI Translation

The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.

Features

AI Translation
  • OE# pins/Suitable for Express Card applications
  • PLL or bypass mode/PLL can dejitter incoming clock
  • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
  • Spread Spectrum Compatible/tracks spreading input clock for low EMI
  • SMBus Interface/unused outputs can be disabled

Applications

AI Translation
  • 6 output PCIe Gen3 zero-delay/fanout buffer