- Pinbelegung
- Footprint
RENESAS 9DB633AGLF
| Hersteller | |
| Herst.-Teilenr. | 9DB633AGLF |
| LCSC-Nr. | C1540616 |
| Verp. | TSSOP-28 |
| Kundennummer | |
| Hauptmerkm. | 3.3V 6 TSSOP-28 Application Specific Clock/Timing RoHS |
| Datenblatt | RENESAS 9DB633AGLF |
Produktspezifikationen
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | TSSOP-28 | |
| Voltage - Supply | 3.3V | |
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | - | |
| Operating Temperature | 0℃~+70℃ | |
| Number of outputs | 6 |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | TSSOP-28 | |
| Voltage - Supply | 3.3V |
| Typ | Beschreibung | |
|---|---|---|
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | - | |
| Operating Temperature | 0℃~+70℃ | |
| Number of outputs | 6 |
Beschreibung
The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.
Merkmale
- OE# pins/Suitable for Express Card applications
- PLL or bypass mode/PLL can dejitter incoming clock
- Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
- Spread Spectrum Compatible/tracks spreading input clock for low EMI
- SMBus Interface/unused outputs can be disabled
Anwendungen
- 6 output PCIe Gen3 zero-delay/fanout buffer
| Stk. | E-Preis | Gesamtbetrag |
|---|---|---|
| 1+ | $ 8.2596 | $ 8.26 |
| 10+ | $ 8.0663 | $ 80.66 |
| 30+ | $ 7.9368 | $ 238.10 |
| 100+ | $ 7.8073 | $ 780.73 |
Standardgehäuse50/Full Tube | ||
Produktspezifikationen
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | TSSOP-28 | |
| Voltage - Supply | 3.3V | |
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | - | |
| Operating Temperature | 0℃~+70℃ | |
| Number of outputs | 6 |
| Typ | Beschreibung | |
|---|---|---|
| Kategorie | Integrated Circuits (ICs)/Clock/Timing/Application Specific Clock/Timing | |
| Hersteller | RENESAS | |
| Verp. | TSSOP-28 | |
| Voltage - Supply | 3.3V |
| Typ | Beschreibung | |
|---|---|---|
| Features | Low-jitter clock re-timing/cleaning;Built-in phase-locked loop;Spread spectrum;Output enable/shutdown | |
| Output Frequency(Max) | - | |
| Operating Temperature | 0℃~+70℃ | |
| Number of outputs | 6 |
Beschreibung
The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications.
Merkmale
- OE# pins/Suitable for Express Card applications
- PLL or bypass mode/PLL can dejitter incoming clock
- Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
- Spread Spectrum Compatible/tracks spreading input clock for low EMI
- SMBus Interface/unused outputs can be disabled
Anwendungen
- 6 output PCIe Gen3 zero-delay/fanout buffer
C1540616 EasyEDA-Bibliothek
Compliance & Exportcodes
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Typ | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Typ | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |