MICROCHIP PM8532B-F3EI

The Switchtec PFX/PFX-I PCIe Gen3 fanout switch families comprise high reliability PCIe Base Specification 3.1-compliant switches supporting up to 96 lanes, 24 virtual switch partitions, 48 Non-Transparent Bridges (NTBs), hot- and surprise-plug controllers for each port, advanced error containment and comprehensive diagnostics and debug capabilities. The PFX-I Gen3 PCIe Switch supports the full feature set available on the PFX and operates over an extended industrial temperature range of -40°C ambient to 105°C junction.

• High-Performance Non-Blocking Switches:
  • Up to 174 GB/s switching capacity
  • 96-lane, 80-lane, 64-lane, 48-lane, 32-lane, and 24-lane variants
  • Ports bifurcate from x2 to x16 lanes
  • Up to 48 NTBs assignable to any port
  • Logical Non-Transparent (NT) interconnect allows for larger topologies (up to 256 masters)
  • Supports 1+1 and N+1 failover mechanisms
  • NT address translation using direct windows and multiple sub-windows per BAR
  • Supports multicast groups per port
  • PFX-I supports an extended industrial temperature range TA: -40°C to TJ: 105°C
• Error Containment:
  • Advanced Error Reporting (AER) on all ports
  • Downstream Port Containment (DPC) on all downstream ports
  • Poisoned TLP blocking
  • Completion Timeout Synthesis (CTS) to prevent an error state in an upstream host due to incomplete non-posted transactions
  • Hot- and surprise-plug controllers per port
  • GPIOs configurable for different cable/connector standards
• PCIe Interfaces:
  • Passive, managed and optical cables SFF-8644, SFF-8643, SFF-8639, OCuLink and other connectors
  • SHPC-enabled slot and edge connectors
• Diagnostics and Debug:
  • Transaction Layer Packet (TLP) generator for testing and debugging of links and error handling
  • Real-time eye capture
  • Any-to-any port mirroring for debug purposes
  • External loopback at PHY and TLP layers
  • Errors, statistics, performance, and TLP latency counters
• Highlights:
  • High-reliability PCIe: robust error containment, hot- and surprise-plug controllers per port, end-to-end data integrity protection, ECC protection on RAMs, high-quality, low power SERDES
  • Comprehensive diagnostics and debugging: PCIe generator and analyzer, per-port performance and error counters, multiple loopback modes and real-time eye capture
  • Significant power, cost and board space savings with support for: Up to 48 ports, 48 NTBs and 24 virtual switch partitions
  • Flexible x2, x4, x8 and x16 port bifurcation with no restrictions on configuring ports as either upstream or downstream or on mapping ports to NTBs
• Peripheral I/O Interfaces:
  • Up to 11 Two-Wire Interfaces (TWIs) with SMBus support
  • Up to 2 SFF-8485-compliant SGPIO ports
  • Up to 109 parallel GPIO pins
  • Up to 4 UARTs
  • JTAG and EJTAG interface
• High-Speed I/O:
  • PCIe Gen3 8 GT/s
  • Supports PCIe-compliant link training and manual PHY configuration
• Power Management:
  • Active State Power Management (ASPM)
  • Software controlled power management
• Chiplink Diagnostic Tools:
  • Extensive debug, diagnostics, configuration and analysis tools with an intuitive GUI
  • Access to configuration data, management capabilities and signal integrity analysis tools (such as real-time eye capture)
  • Connects to device over in-band PCIe or sideband signals (UART, TWI and EJTAG)

• data center equipment
• industrial servers
• workstations
• test equipment
• video production and broadcasting equipment
• cellular infrastructure
• access networks
• metro networks
• core networking