TI SN65LVDS93ADGG

The SN65LVDS93A LVDS SerDes (Serializer/Deserializer) transmitter integrates four 7-bit parallel-load serial-output shift registers, one 7× clock multiplier, and five LVDS drivers in a single IC. These features enable synchronous transmission of 28-bit single-ended LVTTL data over five balanced-pair conductors for reception by a compatible receiver such as the SN65LVDS94.

During data transmission, data bits D0 through D27 are all loaded into the registers on the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The CLKIN frequency is multiplied by a ratio of 7 and then used to serially unload the data registers in 7-bit time slices. The four serial data streams and the phase-locked clock (CLKOUT) are then output to the LVDS output drivers. The CLKOUT frequency is the same as the input clock (CLKIN).

The SN65LVDS93A requires no external components and minimal to no control. The data bus at the transmitter input is identical to the data bus at the receiver output, making the data transfer transparent to the user. The only user-controllable options are selecting the rising clock edge (apply logic high to CLKSEL) or falling edge (apply logic low to CLKSEL), and the use of the shutdown/clear (SHTDN) signal. SHTDN is an active-low input that disables the clock and shuts down the LVDS output drivers to reduce power consumption. When held low, all internal registers are cleared (held low).

The SN65LVDS93A operates over an ambient air temperature range of -40°C to 85°C.

FlatLink™ is an LVDS SerDes data transmission system. The SN65LVDS93A takes in three (or four) data words each containing seven single-ended data bits, and converts this to an LVDS serial output. Each serial output runs at seven times that of the parallel data rate. The deserializer (receiver) device operates in the reverse manner. The three (or four) LVDS serial inputs are transformed back to the original 7-bit parallel single-ended data. FlatLink devices are available in 21:3 or 28:4 SerDes ratios. • The 21-bit devices are designed for 6-bit RGB video for a total of 18 bits in addition to 3 extra bits for horizontal synchronization, vertical synchronization, and data enable. • The 28-bit devices are intended for 8-bit RGB video applications. Again, the extra 4 bits are for horizontal synchronization, vertical synchronization, data enable, and the remaining is the reserved bit. These 28-bit devices can also be used in

• Industrial temperature range -40°C to 85°C LVDS display SerDes interface, directly connectable to LCD display panels with integrated LVDS
• Package options: 4.5mm×7mm BGA and 8.1mm×14mm TSSOP
• 1.8V to 3.3V tolerant data inputs, directly connectable to low-power, low-voltage applications and graphics processors
• Transmission rate up to 135Mpps (megapixels per second); pixel clock frequency range 10MHz to 135MHz
• Suitable for display resolutions from HVGA to HD with low EMI
• Single 3.3V supply operation; 170mW typical power consumption at 75MHz
• 28 data channels and clock input LVTTL to 4 data channels and clock output low-voltage differential
• Power consumption less than 1mW when disabled
• Selectable rising or falling clock edge triggered input
• ESD: 5kV HBM
• Spread Spectrum Clock (SSC) support
• Compatible with all OMAP™ 2x, OMAP3x, and DaVinci™ application processors

• LCD display panel driver
• UMPC and netbook
• Digital photo frame