MICROCHIP AT91SAM9N12-CU

Based on the ARM926EJ-S processor, the SAM9N12/CN11/CN12 devices offer the frequently-requested combination of user interface functionality and high data rate connectivity, with LCD Controller, resistive touch-screen, multiple UARTs, SPI, I2C, full-speed USB Host and Device and SDIO. The SAM9N12/CN11/CN12 support the latest generation of LPDDR/DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multilayer bus architecture associated with eight DMA channels and distributed memory – including a 32-Kbyte SRAM – sustains the high bandwidth required by the processor and the high-speed peripherals. The SAM9CN12/CN11 offers on-chip hardware accelerators with DMA support that enable high-speed data encryption and authentication of transferred data or applications. Supported standards are up to 256-bit AES, and FIPS Publication 180-2 compliant SHA1 and SHA256. A True Random Number Generator is embedded for key generation and exchange protocols. The devices also feature fuse bits for crypto key (SAM9CN12), user configuration (SAM9N12 and SAM9CN11) and device configuration (all). The SAM9CN12 includes a secured Boot ROM; the SAM9N12 and SAM9CN11 include a standard Boot ROM. The I/Os support 1.8V or 3.3V operation and are independently configurable for the memory interface and peripheral I/Os. This feature eliminates the need for any external level shifters, while 0.8 ball pitch packages lower PCB cost and complexity. The SAM9N12/CN11/CN12 power management controllers feature efficient clock gating and a battery backup section that minimizes power consumption in active and standby modes.

• Core: ARM926EJ-S ARM Thumb Processor running up to 400 MHz, 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
• Memories:
  • One 128-Kbyte internal ROM embedding standard or secure bootstrap routine.
  • One 32-Kbyte internal SRAM, single-cycle access at system speed
  • 32-bit External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static Memories
  • MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error Correcting Code (PMECC)
  • System running up to 133 MHz
  • Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real Time Clock
  • Boot Mode Select Option, Remap Command
  • Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
  • Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator, one PLL for the system and one PLL optimized for USB
  • Six 32-bit-layer AHB Bus Matrix
  • Dual Peripheral Bridge with dedicated programmable clock
  • One dual port 8-channel DMA Controller
  • Advanced Interrupt Controller and Debug Unit
  • Two Programmable External Clock Signals
  • Shut Down Controller with four 32-bit battery backup registers
  • Clock Generator and Power Management Controller
  • Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
• Peripherals:
  • LCD Controller
  • USB Device Full Speed with dedicated On-Chip Transceiver
  • USB Host Full Speed with dedicated On-Chip Transceiver
  • One High speed SD card and SDIO Host Controller
  • Two Master/Slave Serial Peripheral Interfaces
  • Two Three-channel 32-bit Timer/Counters
  • One Synchronous Serial Controller
  • One Four-channel 16-bit PWM Controller
  • Two Two-wire Interfaces
  • Four USARTs, two UARTs, one DBGU
  • One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive Touch screen support
  • Crystal Failure Detection
  • Independent Watchdog
  • Power-on Reset Cells
  • Write Protection Registers
  • SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2
• I/O:
  • Four 32-bit Parallel Input/Output Controllers
  • 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
  • Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input
  • Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output