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TI SN74AHCT74PWR
| Manufacturer | |
| MPN | SN74AHCT74PWR |
| LCSC Part # | C141308 |
| Packaging | TSSOP-14 |
| Customer # | |
| Key Attributes | QUADRUPLE 2-INPUT POSITIVE-NAND GATES |
| Datasheet | TI SN74AHCT74PWR |
| RoHS Compliance | 2 documents available |
| Alternative Parts | 5 |
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | TSSOP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74AHCT Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 5ns | |
| Quiescent Current | 2uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.8ns@5V,50pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | TSSOP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74AHCT Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 2 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 5ns | |
| Quiescent Current | 2uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.8ns@5V,50pF | |
| Trigger Type | Rising Edge |
Introduction
The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE(overline)) or clear (CLR(overline)) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Features
- Inputs Are TTL-Voltage Compatible
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 5+ | $ 0.1077 | $ 0.54 |
| 50+ | $ 0.1051 | $ 5.26 |
| 150+ | $ 0.1033 | $ 15.50 |
| 500+ | $ 0.1015 | $ 50.75 |
Standard Packaging2000/Full Reel | ||
Products Specifications
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | TSSOP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74AHCT Series | |
| Synchronous/Asynchronous | Asynchronous | |
| Number of Elements | 2 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 5ns | |
| Quiescent Current | 2uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.8ns@5V,50pF | |
| Trigger Type | Rising Edge |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Logic/Flip Flops | |
| Manufacturer | TI | |
| Packaging | TSSOP-14 | |
| Voltage - Supply | 4.5V~5.5V | |
| Number of Bits per Element | 1 | |
| Output Type | Complementary | |
| Operating Temperature | -40℃~+125℃ | |
| Series | 74AHCT Series | |
| Synchronous/Asynchronous | Asynchronous |
| Type | Description | |
|---|---|---|
| Number of Elements | 2 | |
| Current - Output High(IOH) | 8mA | |
| Current - Output Low(IOL) | 8mA | |
| Setup Time | 5ns | |
| Quiescent Current | 2uA | |
| Hold Time | 0ns | |
| Propagation Delay | 8.8ns@5V,50pF | |
| Trigger Type | Rising Edge |
Introduction
The ’AHCT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE(overline)) or clear (CLR(overline)) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
Features
- Inputs Are TTL-Voltage Compatible
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
C141308 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Type | Details |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
Alternative Parts
| MPN | Manufacturer | Alternative Type | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|---|
| SN74AHCT74QPWRQ1 | TI | Similar | TSSOP-14 | 845 | $ 0.3755 | ||
| 74AHCT74PW,118 | Nexperia | Similar | TSSOP-14 | 165 | $ 0.172 | ||
| 74VHC74FT(BJ) | TOSHIBA | Similar | TSSOP14B | 945 | $ 0.2424 | ||
| SN74LV74APWR | TI | Similar | TSSOP-14 | 1,985 | $ 0.1383 | ||
| SN74AHC74QPWRG4Q1 | TI | Similar | TSSOP-14 | 9 | $ 1.1882 |