NXP MPC5553MVR132

The MPC5553 microcontroller (MCU) is a member of the MPC5500 microcontroller family, built on Power Architecture embedded technology. This product family features numerous new characteristics that, combined with high-performance CMOS technology, significantly reduce per-feature cost and substantially improve performance compared to the MPC500 series. The device's main processor core complies with the Power Architecture embedded category and is 100% user-mode compatible with the original PowerPC instruction set (including floating-point libraries). Embedded architecture enhancements improve performance for embedded applications; the core adds instructions beyond the original PowerPC instruction set, including DSP instructions. The MPC5500 family, combined with high-performance CMOS technology, delivers significant performance improvements over the MPC565. The MPC5553 features a two-level memory hierarchy with on-chip memory and an external bus interface supporting a wide range of standard memory types. The device integrates multiple levels of timer processing units, various communication interfaces, ADCs, a system integration unit, and a fast Ethernet controller to meet diverse functional requirements.

• Based on Power Architecture embedded technology combined with high-performance CMOS technology
• Main processor core compliant with Power Architecture embedded category, 100% user-mode compatible with the original PowerPC instruction set (including floating-point library)
• Core features additional instructions including DSP to enhance embedded application performance
• Two-level memory hierarchy: on-chip 8KB unified cache, 64KB on-chip SRAM, 1.5MB internal flash
• External bus interface supports most standard memory types used by the MPC5xx series
• Complex I/O timer functions implemented by the eTPU engine, controlling 32 hardware channels
• eTPU enhancements over TPU include: 24-bit timers, dual-action hardware channels, variable number of parameters per channel, angle clock hardware, additional control and arithmetic instructions, and support for high-level programming language
• Low-complexity timer functions implemented by eMIOS with 24 hardware channels
• eMIOS supports single-action, dual-action, PWM, and modulo counter operations; supports edge-aligned and center-aligned PWM with motor control capability
• Off-chip communication supports FlexCAN, enhanced DSPI, and eSCI
• Integrated eQADC; 324 and 416 package versions support 40 channels
• Integrated SIU supporting full-chip configuration, pad configuration, GPIO control, external interrupt, and reset control
• Integrated SIU_DISR providing eQADC trigger source multiplexing and external interrupt signal multiplexing
• Integrated RISC-based FEC controller supporting 10 Mbps and 100 Mbps Ethernet/IEEE 802.3 networks
• FEC compatible with three different standard MAC PHY interfaces; supports 10/100 Mbps MII interface and 10 Mbps-only 7-wire interface
• FEC includes built-in transmit and receive message FIFOs with DMA support

• Embedded applications