MICROCHIP AT32UC3C2128C-A2ZT

The AT32UC3C is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies up to 50 MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Using the Secure Access Unit (SAU) together with the MPU provides the required security and integrity. Higher computation capabilities are achievable either using a rich set of DSP instructions or using the floating-point instructions. The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access. For applications requiring additional memory, an external memory interface is provided on AT32UC3C0 derivatives. The Memory Direct Memory Access controller (MDMA) enables transfers of block of data from memories to memories without processor involvement. The Peripheral Direct Memory Access (PDCA) controller enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3C incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device.

• High Performance, Low Power 32-bit AVR Microcontroller
  • Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
  • Built-in Floating-Point Processing Unit (FPU)
  • Read-Modify-Write Instructions and Atomic Bit Manipulation
  • Performing 1.49 DMIPS / MHz
  • Up to 68 DMIPS Running at 50 MHz from Flash (1 Wait-State)
  • Up to 37 DMIPS Running at 25 MHz from Flash (0 Wait-State)
  • Memory Protection Unit
• Multi-hierarchy Bus System
  • High-Performance Data Transfers on Separate Buses for Increased Performance
  • 16 Peripheral DMA Channels Improves Speed for Peripheral Communication
• Internal High-Speed Flash
  • 512 Kbytes, 256 Kbytes, 128 Kbytes Versions
  • Single Cycle Access up to 25 MHz
  • FlashVault™ Technology Allows Pre-programmed Secure Library Support for End User Applications
  • Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
  • 10,000 Write Cycles, 15-year Data Retention Capability
  • Flash Security Locks and User Defined Configuration Area
• Internal High-Speed SRAM, Single-Cycle Access at Full Speed
  • 64 Kbytes (512 KB and 256 KB Flash), 32 Kbytes (128 KB Flash)
  • 4 Kbytes on the Multi-Layer Bus System (HSB RAM)
• External Memory Interface on AT32UC3C0 Derivatives
  • SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
• Interrupt Controller
  • Autovectored Low Latency Interrupt Service with Programmable Priority
• System Functions
  • Power and Clock Manager
  • Internal 115KHz (RCSYS) and 8MHz/1MHz (RC8M) RC Oscillators
  • One 32 KHz and Two Multipurpose Oscillators
  • Clock Failure detection
  • Two Phase-Lock-Loop (PLL) allowing Independent CPU Frequency from USB or CAN Frequency
• Windowed Watchdog Timer (WDT)
• Asynchronous Timer (AST) with Real-Time Clock Capability
  • Counter or Calendar Mode Supported
• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency
• Ethernet MAC 10/100 Mbps interface
  • 802.3 Ethernet Media Access Controller
  • Supports Media Independent Interface (MII) and Reduced MII (RMII)
• Universal Serial Bus (USB)
  • Device 2.0 and Embedded Host Low Speed and Full Speed
  • Flexible End-Point Configuration and Management with Dedicated DMA Channels
  • On-chip Transceivers Including Pull-Ups
• One 2-channel Controller Area Network (CAN)
  • CAN2A and CAN2B protocol compliant, with high-level mailbox system
  • Two independent channels, 16 Message Objects per Channel
• One 4-Channel 20-bit Pulse Width Modulation Controller (PWM)
  • Complementary outputs, with Dead Time Insertion
  • Output Override and Fault Protection
• Two Quadrature Decoders
• One 16-channel 12-bit Pipelined Analog-To-Digital Converter (ADC)
  • Dual Sample and Hold Capability Allowing 2 Synchronous Conversions
  • Single-Ended and Differential Channels, Window Function
• Two 12-bit Digital-To-Analog Converters (DAC), with Dual Output Sample Syste
• Four Analog Comparators
• Six 16-bit Timer/Counter (TC) Channels
  • External Clock Inputs, PWM, Capture and Various Counting Capabilities
• One Peripheral Event Controller
  • Trigger Actions in Peripherals Depending on Events Generated from Peripherals or from Input Pins
  • Deterministic Trigger
  • 34 Events and 22 Event Actions
• Five Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
  • Independent Baudrate Generator, Support for SPI, LIN, IrDA and ISO7816 interfaces
  • Support for Hardware Handshaking, RS485 Interfaces and Modem Line
• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
• Three Master and Three Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible
• QTouch Library Support
  • Capacitive Touch Buttons, Sliders, and Wheels
  • QTouch and QMatrix Acquisition
• On-Chip Non-intrusive Debug System
  • Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
  • aWire™ single-pin programming trace and debug interface muxed with reset pin
  • NanoTrace™ provides trace capabilities through JTAG or aWire interface
• 3 package options
  • 64-pin QFN/TQFP (45 GPIO pins)
  • 100-pin TQFP (81 GPIO pins)
  • 144-pin LQFP (123 GPIO pins)
• Two operating voltage ranges:
  • Single 5V Power Supply
  • Single 3.3V Power Supply