TI SN74LS92N

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a threestage binary counter for which the count cycle length is divide-by-five for the '90A and LS90, divide-by-six for the '92A and LS92, and the divide-by-eight for the '93A and LS93. All of these counters have a gated zero reset and the '90A and LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications. To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the A output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the QD output to the CKA input and applying the input count to the CKB input which gives a divide-byten square wave at output QA.

• Gated zero-reset on all series counters
• '90A and LS90 include additional gated set-to-nine inputs
• Port connections available for maximum count lengths of decade, divide-by-twelve, and 4-bit binary
• '90A or LS90 configured for symmetrical divide-by-ten operation via port connection, with divide-by-ten square wave available at QA output
• Multiple package types and series options available
• Typical power dissipation: 145mW for '90A, 130mW for '92A, 45mW for LS series
• Maximum ratings: supply voltage VCC = 7V, input voltage = 5.5V, interemitter voltage = 5.5V, storage temperature range -65℃ to 150℃
• Operating free-air temperature range: -55℃ to 125℃ for SN54 series, 0℃ to 70℃ for SN74 series
• QA output drives CKB input while maintaining full fan-out capability

• BCD nine's complement related applications
• General-purpose digital counting and frequency division scenarios