Alliance Memory AS4C256M16D4-83BCN

The DDR4 SDRAM is a high-speed dynamic random-access memory internally organized with eight-banks (2 bank groups each with 4 banks). The DDR4 SDRAM uses a 8n prefetch architecture to achieve high-speed operation. The 8n prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write operation for the DDR4 SDRAM consists of a single 8n-bit wide, four clock data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.

• JEDEC Standard Compliant
• Fast clock rate: 1200/1333MHz
• Power supplies: - VDD & VDDQ = +1.2V ± 0.06V - VPP = +2.5V - 0.125V / +0.25V
• Operating temperature range: - Commercial: TC = 0 ~ 95℃ - Industrial: TC = -40 ~ 95℃
• Supports JEDEC clock jitter specification
• Bidirectional differential data strobe, DQS & DQS#
• Differential Clock, CK & CK#
• 8 internal banks: 2 groups of 4 banks each
• Separated IO gating structures by Bank Group
• 8n-bit prefetch architecture
• Precharge & Active power down
• Auto Refresh and Self Refresh
• Low-power auto self refresh (LPASR)
• Self Refresh Abort
• Fine Granularity Refresh
• Dynamic ODT (RTT_PARK & RTT_Nom & RTT_WR)
• Write Leveling
• DQ Training via MPR
• Programmable preamble is supported both of 1tCK and 2tCK mode
• Command/Address (CA) Parity
• Data bus write cyclic redundancy check (CRC)
• Boundary Scan Mode
• Internal VREFDQ Training
• Read Preamble Training
• Control Gear Down Mode
• Per DRAM Addressability (PDA)
• Output Driver Impedance Control
• Dynamic on-die termination (ODT)
• Input Data Mask (DM) and Data Bus Inversion (DBI)
• ZQ Calibration
• Command/Address latency (CAL)
• Asynchronous Reset
• DLL enable/disable
• Burst Length (BL8/BC4/BC4 or 8 on the fly)
• Burst type: Sequential / Interleave
• CAS Latency (CL)
• CAS Write Latency (CWL)
• Additive Latency (AL): 0, CL - 1, CL - 2
• Average refresh period - 8192 cycles/64ms (7.8us at -40℃ ≤ TC ≤ +85℃) - 8192 cycles/32ms (3.9us at +85℃ ≤ TC ≤ +95℃)
• Data Interface: Pseudo Open Drain (POD)
• RoHS compliant
• Hard post package repair (hPPR)
• Soft post package repair (sPPR)
• Package: Pb Free and Halogen Free - 96-ball 7.5x13.5x1.2mm FBGA