MICROCHIP M7A3P1000-FG144I

ProASIC3 is Actel's third-generation flash FPGA family, surpassing the ProASICPLUS family in performance, density, and features. The nonvolatile flash technology gives ProASIC3 devices the advantages of security, low power consumption, single-chip operation, and instant-on capability. The devices are reprogrammable and offer time-to-market advantages with ASIC-level unit costs. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. ProASIC3 devices provide 1 kbit of on-chip reprogrammable nonvolatile FlashROM memory, along with integrated PLL-based clock conditioning circuits. The A3P015 and A3P030 devices do not support PLL or RAM. ProASIC3 devices offer up to 1 M system gates.

• System gate capacity from 15 k to 1 M
• Up to 144 kbit true dual-port SRAM
• Up to 300 user I/Os
• 130 nm, 7-layer metal (6-layer copper), flash-based CMOS process
• Live-at-power-up Grade 0 support
• Single-chip solution
• Retains programmed design when powered down
• 350 MHz system performance
• 3.3 V, 66 MHz 64-bit PCI support
• Secure in-system programming via JTAG (with on-chip 128-bit AES decryption, IEEE 1532 compliant)
• FPGA content security protection via FlashLock
• Low-power core voltage
• System support down to 1.5 V
• Low-impedance flash switches
• Segmented, hierarchical routing and clock architecture
• 700 Mbps DDR, LVDS-capable I/O support
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operation
• Wide-range supply voltage per JESD8-B, I/O operation from 2.7 V to 3.6 V
• Selectable I/O bank voltages — up to 4 banks per device
• Single-ended I/O standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V input
• Differential I/O standards: LVPECL, LVDS, B-LVDS, and M-LVDS
• I/O registers on input, output, and enable paths
• Hot-swap and cold-spare I/O support
• Programmable output slew rate and drive strength
• Weak pull-up/pull-down
• IEEE 1149.1 boundary scan test
• Pin-compatible packages within ProASIC3 family
• Six clock conditioning circuit blocks, one with integrated PLL
• Configurable phase shift, multiply/divide, delay capability, and external feedback
• Wide input frequency range
• 1 kbit FlashROM user non-volatile memory
• SRAM and FIFO with variable aspect ratio 4,608-bit RAM blocks
• True dual-port SRAM
• M1 and M7 ProASIC3 devices support Cortex-M1 and CoreMP7 soft processors, with or without debug