TI ADC08B200CIVS/NOPB
| Fabricante | |
| N.º de pieza fab. | ADC08B200CIVS/NOPB |
| Nº LCSC | C701490 |
| Emb. | TQFP-48(7x7) |
| Número de Cliente | |
| Atrib. clave | 8-Bit, 200 MSPS A/D Converter with Capture Buffer |
| Hoja de Datos | TI ADC08B200CIVS/NOPB |
| Cumplimiento RoHS | 2 documentos disponibles |
Especificaciones del Producto
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Fabricante | TI | |
| Emb. | TQFP-48(7x7) | |
| Operating Temperature | -40℃~+105℃ | |
| Interface | Parallel port | |
| Quiescent Current (Iq) | 650uA | |
| Voltage - Supply | 3V~3.6V | |
| Number of Channels | 1 | |
| Integral non - linearity | 1.3LSB | |
| Voltage Reference | External | |
| Clock/Oscillator | External | |
| Clock Frequency | 1MHz~210MHz;15MHz~105MHz | |
| Features | FIFO buffer;Soft reset;Power-on reset | |
| Resolution(Bits) | 200MHz;8 | |
| S/N Ratio | 46.3dB | |
| ADC architecture | - | |
| Programmable Gain | Not supported |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Fabricante | TI | |
| Emb. | TQFP-48(7x7) | |
| Operating Temperature | -40℃~+105℃ | |
| Interface | Parallel port | |
| Quiescent Current (Iq) | 650uA | |
| Voltage - Supply | 3V~3.6V | |
| Number of Channels | 1 | |
| Integral non - linearity | 1.3LSB |
| Tipo | Descripción | |
|---|---|---|
| Voltage Reference | External | |
| Clock/Oscillator | External | |
| Clock Frequency | 1MHz~210MHz;15MHz~105MHz | |
| Features | FIFO buffer;Soft reset;Power-on reset | |
| Resolution(Bits) | 200MHz;8 | |
| S/N Ratio | 46.3dB | |
| ADC architecture | - | |
| Programmable Gain | Not supported |
Descripción
The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock.
Características
- Single-Ended Input
- Selectable Capture Buffer Size
- PLL for Clock Multiplication
- Reference Ladder Top and Bottom Accessible
- Linear Power Scaling with Sample Rate
- FPGA Training Pattern
- AEC-Q100 Grade 2 Qualified
- Power-Down Feature
Aplicaciones
- Laser Ranging
- RADAR Pulse Capturing
| Cant. | Prec. unit. | Importo total |
|---|---|---|
| 1+ | $ 23.9164 | $ 23.92 |
| 30+ | $ 23.0545 | $ 691.64 |
Encapsulado Estándar250/Full Tray | ||
Especificaciones del Producto
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Fabricante | TI | |
| Emb. | TQFP-48(7x7) | |
| Operating Temperature | -40℃~+105℃ | |
| Interface | Parallel port | |
| Quiescent Current (Iq) | 650uA | |
| Voltage - Supply | 3V~3.6V | |
| Number of Channels | 1 | |
| Integral non - linearity | 1.3LSB | |
| Voltage Reference | External | |
| Clock/Oscillator | External | |
| Clock Frequency | 1MHz~210MHz;15MHz~105MHz | |
| Features | FIFO buffer;Soft reset;Power-on reset | |
| Resolution(Bits) | 200MHz;8 | |
| S/N Ratio | 46.3dB | |
| ADC architecture | - | |
| Programmable Gain | Not supported |
| Tipo | Descripción | |
|---|---|---|
| Categoría | Integrated Circuits (ICs)/Data Acquisition/Analog to Digital Converters (ADC) | |
| Fabricante | TI | |
| Emb. | TQFP-48(7x7) | |
| Operating Temperature | -40℃~+105℃ | |
| Interface | Parallel port | |
| Quiescent Current (Iq) | 650uA | |
| Voltage - Supply | 3V~3.6V | |
| Number of Channels | 1 | |
| Integral non - linearity | 1.3LSB |
| Tipo | Descripción | |
|---|---|---|
| Voltage Reference | External | |
| Clock/Oscillator | External | |
| Clock Frequency | 1MHz~210MHz;15MHz~105MHz | |
| Features | FIFO buffer;Soft reset;Power-on reset | |
| Resolution(Bits) | 200MHz;8 | |
| S/N Ratio | 46.3dB | |
| ADC architecture | - | |
| Programmable Gain | Not supported |
Descripción
The ADC08B200 is a high speed analog-to-digital converter (ADC) with an integrated capture buffer. The 8-bit, 200 MSPS A/D core is based upon the proven ADC08200 with integrated track-and-hold and is optimized for low power consumption. This device contains a selectable size capture buffer of up to 1,024 bytes that allows fast capture of an input signal with a slower readout rate. An on-chip clock PLL circuit provides the option of on-chip clock rate multiplication to provide the high speed sampling clock.
Características
- Single-Ended Input
- Selectable Capture Buffer Size
- PLL for Clock Multiplication
- Reference Ladder Top and Bottom Accessible
- Linear Power Scaling with Sample Rate
- FPGA Training Pattern
- AEC-Q100 Grade 2 Qualified
- Power-Down Feature
Aplicaciones
- Laser Ranging
- RADAR Pulse Capturing
C701490 Biblioteca EasyEDA
Cumplimiento & Códigos de Exportación
| Tipo | Detalles |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |
| Tipo | Detalles |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | EAR99 |
| CNHTS | 8542399000 |
| USHTS | 8542390001 |
| TARIC | 8542399000 |
| Tipo | Detalles |
|---|---|
| CAHTS | 8542390000 |
| BRHTS | 85423999 |
| INHTS | 85423900 |
| MXHTS | 8542.39.99 |

