Infineon CYT4BB5CEBQ0AEEGS

CYT3BB/4BB is a family of TRAVEO T2G microcontrollers targeted at automotive systems such as high-end body-control units. CYT3BB/4BB has one or two Arm Cortex -M7 CPUs for primary processing, and an Arm Cortex M0+ CPU for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area Network with Flexible Data rate (CAN FD), Local Interconnect Network (LIN), and Ethernet. TRAVEO T2G devices are manufactured on an advanced 40 - nm process. CYT3BB/4BB incorporates a low - power flash memory, multiple high - performance analog and digital peripherals, and enables the creation of a secure computing platform.

• CPU subsystem
  • One or two 250 - MHz 32 - bit Arm Cortex -M7 CPUs, each with single - cycle multiply, single/double - precision floating point unit (FPU), 16 - KB data cache, 16 - KB instruction cache, memory protection unit (MPU), 16 - KB instruction and 16 - KB data tightly - coupled memories (TCM)
  • 100 - MHz 32 - bit Arm Cortex M0+ CPU with single - cycle multiply, MPU
  • Inter - processor communication in hardware
  • Three DMA controllers: Peripheral DMA controller #0 (P - DMA0) with 100 channels, Peripheral DMA controller #1 (P - DMA1) with 58 channels, Memory DMA controller (M - DMA0) with 8 channels
• Integrated memories
  • Read - While - Write (RWW) allows updating the code - flash/work - flash while executing from it
  • Single - and dual - bank modes (specifically for Firmware update Over The Air [FOTA])
  • Flash programming through SWD/JTAG interface
  • 768 KB of SRAM with selectable retention granularity
• Cryptography engine
  • Supports enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
  • Secure boot and authentication using digital signature verification and fast secure boot
  • AES: 128 - bit blocks, 128 -/192 -/256 - bit keys
  • 3DES: 64 - bit blocks, 64 - bit key
  • Vector unit supporting asymmetric key cryptography such as Rivest - Shamir - Adleman (RSA) and Elliptic Curve (ECC)
  • SHA - 1/2/3: SHA - 512, SHA - 256, SHA - 160 with variable length input data
  • CRC: supports CCITT CRC16 and IEEE - 802.3 CRC32
  • True random number generator (TRNG) and pseudo random number generator (PRNG)
  • Galois/Counter Mode (GCM)
• Functional safety for ASIL - B
  • Memory protection unit (MPU)
  • Shared memory protection unit (SMPU)
  • Peripheral protection unit (PPU)
  • Watchdog timer (WDT)
  • Multi - counter watchdog timer (MCWDT)
  • Low - voltage detector (LVD)
  • Brown - out detection (BOD)
  • Over - voltage detection (OVD)
  • Clock supervisor (CSV)
  • Hardware error correction (SECDED ECC) on all safety - critical memories (SRAM, flash, TCM)
  • Low - power 2.7 - V to 5.5 - V operation
  • Low - power Active, Sleep, Low - power Sleep, DeepSleep, and Hibernate modes for fine - grained power management
  • Configurable options for robust BOD: Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA, One threshold level (1.1 V) for BOD on VCCD
• Wakeup
  • Up to two pins to wake from Hibernate mode
  • Up to 220 GPIO pins to wake from Sleep modes
  • Event Generator, SCB, Watchdog Timer, RTC alarms to wake from DeepSleep modes
• Clocks
  • Internal main oscillator (IMO)
  • Internal low - speed oscillator (ILO)
  • External crystal oscillator (ECO)
  • Watch crystal oscillator (WCO)
  • Phase - locked loop (PLL)
  • Frequency - locked loop (FLL)
• Communication interfaces
  • Up to eight CAN FD channels: Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and transceivers, Compliant with ISO 11898 - 1:2015, Supports all the requirements of Bosch CAN FD Specification V1.0 for non - ISO CAN FD, ISO 16845:2015 certificate available
  • Up to 11 runtime - reconfigurable serial communication block (SCB) channels, each configurable as I2C, SPI, or UART
  • Up to 16 independent LIN channels: LIN protocol compliant with ISO 17987
  • One 10/100 Mbps Ethernet MAC interface conforming to IEEE - 802.3bw: Supports the following PHY interfaces: Media - independent interface (MII), Reduced media - independent interface (RMII), Compliant with IEEE - 802.1BA Audio Video Bridging (AVB), Compliant with IEEE - 1588 Precision Time Protocol (PTP)
• External memory interface
  • One SPI (Single, Dual, Quad, or Octal) or HYPERBUS interface
  • On - the - fly encryption and decryption
  • Execute - in - place (XIP) from external memory
• SDHC interface
  • One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure Digital (SD), or Secure Digital Input Output (SDIO): Compliant with eMMC 5.1, SD 6.0, and SDIO 4.10 specifications
  • Data rates up to SD High Speed 50 MHz, or eMMC 52 - MHz DDR
• Audio interface
  • Three inter - IC sound (I2S) interfaces for connecting digital audio devices
  • I2S, left justified, or time division multiplexed (TDM) audio formats
  • Independent transmit or receive operation, each in master or slave mode
• Timers
  • Up to 75 16 - bit and eight 32 - bit timer/counter pulse - width modulator (TCPWM) blocks: Up to 12 16 - bit counters for motor control, Up to 63 16 - bit counters and eight 32 - bit counters for regular operations, Supports timer, capture, quadrature decoding, pulse - width modulation (PWM), PWM with dead time (PWM_DT), pseudo - random PWM (PWM_PR), and shift - register (SR) modes
  • Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep: Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion, etc.)
• Real time clock (RTC)
  • Year/Month/Date, Day - of - week, Hour:Minute:Second fields
  • 12 - and 24 - hour formats
  • Automatic leap - year correction
• I/O
  • Up to 220 programmable I/Os
  • Three I/O types: GPIO