Nexperia NPIC6C596D,118

The NPIC6C596 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR(overline) input. A LOW on MR resets both the shift register and storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. To provide additional hold time in cascaded applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor whenever the output enable input (OE(overline)) is LOW. A HIGH on OC(overline) causes the outputs to assume a high-impedance OFF-state. Operation of the OE(overline) input does not affect the state of the registers.

The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS transistors designed for use in systems that require moderate load power such as LEDs. Integrated voltage clamps in the outputs provide protection against inductive transients making the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads.

• Specified from -40 ℃ to +125 ℃
• Low RDSon
• Eight Power EDNMOS transistor outputs of 100 mA continuous current
• 250 mA current limit capability
• Output clamping voltage 33 V
• 30 mJ avalanche energy capability
• Enhanced cascading for multiple stages
• All registers cleared with single input
• Low power consumption
• ESD protection:
  • HBM JDS-001 Class 2 exceeds 2500 V
  • CDM JESD22-C101E exceeds 1000 V

• LED sign
• Graphic status panel
• Fault status indicator