TI 5962-8752501MCA

The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE(overline)) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE(overline) and CLR(overline) are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.

• Operating supply voltage range: 4.5V to 5.5V
• Inputs rated up to 5.5V
• Maximum propagation delay tpd of 10.5ns at 5V
• TTL-compatible input voltage levels
• Maximum rated supply voltage range: -0.5V to 7V
• Maximum rated input voltage range: -0.5V to VCC+0.5V
• Maximum rated output voltage range: -0.5V to VCC+0.5V
• Input clamp current range: ±20mA
• Output clamp current range: ±20mA
• Continuous output current range: ±50mA
• Continuous current through VCC or GND: ±200mA
• Thermal resistance by package: D package 86°C/W, DB package 96°C/W, N package 80°C/W, NS package 76°C/W, PW package 113°C/W
• Storage temperature range: -65°C to 150°C
• All unused inputs must be tied to VCC or GND for proper device operation
• Multiple package options: J, W, FK packages for SN54ACT74; D, DB, N, NS, PW packages for SN74ACT74