RENESAS 74ALVC16841APA

This 20-bit bus interface D-type latch is manufactured using advanced dual-metal CMOS technology. The ALVC16841 features three-state outputs and is specifically designed to drive high-capacitance, relatively low-impedance loads. The device is particularly suited for implementing buffer registers, unidirectional bus drivers, and working registers.

The ALVC16841 can be used as two 10-bit latches or one 20-bit latch. The 20 latches are transparent D-type latches. The device features non-inverting data (D) inputs and provides true data at its outputs. When the latch enable (1LE or 2LE) input is HIGH, the Q outputs of the corresponding 10-bit latch follow the D inputs. When LE transitions LOW, the Q outputs are latched at the level established by the D inputs.

The output enable (1OE or 2OE) inputs can be used to place the outputs of the corresponding 10-bit latch into either a normal logic state (HIGH or LOW logic level) or a high-impedance state. In the high-impedance state, the outputs neither significantly load nor drive the bus lines. OE does not affect the internal operation of the latches. While the outputs are in the high-impedance state, previously stored data can be retained or new data can be entered.

The ALVC16841 is designed with ±24mA output drivers. These drivers are capable of driving moderate to heavy loads while maintaining speed performance.

• 0.5-micron CMOS technology
• Typical t_SK(O) (output skew) < 250ps
• ESD > 2000V per MIL-STD-883 Method 3015; ESD > 200V using machine model (C = 200pF, R = 0)
• SSOP (0.635mm pitch), TSSOP (0.50mm pitch), and TVSOP (0.40mm pitch) packages
• Extended commercial temperature range: -40°C to +85°C
• VCC = 3.3V ± 0.3V, normal range
• VCC = 2.7V to 3.6V, extended range
• VCC = 2.5V ± 0.2V
• CMOS power level (typical quiescent 0.4μW)
• Rail-to-rail output swing for increased noise margin
• ALVC16841 drive characteristics: high output drivers: ±24mA for heavy loads

• 3.3V high-speed systems
• 3.3V and below computing systems