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EDA ModelsEasyEDA
RENESAS R5F565NCDGFP#10
| Manufacturer | |
| MPN | R5F565NCDGFP#10 |
| LCSC Part # | C3207944 |
| Packaging | LFQFP-100(14x14) |
| Customer # | |
| Key Attributes | RXv2 32 Bit 120MHz LFQFP-100(14x14) Microcontrollers RoHS |
| Datasheet | RENESAS R5F565NCDGFP#10 |
| Alternative Parts | 20 |
Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | RENESAS | |
| Packaging | LFQFP-100(14x14) | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 12bit | |
| Number of I/O | 78 | |
| Operating Temperature | -40℃~+105℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 2.7V~3.6V | |
| EEPROM | 32KB | |
| Program Storage Size | 1.5MB | |
| CPU Core | RXv2 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 120MHz | |
| Oscillator Type | Built-in |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | RENESAS | |
| Packaging | LFQFP-100(14x14) | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 12bit | |
| Number of I/O | 78 | |
| Operating Temperature | -40℃~+105℃ | |
| Program Memory Type | FLASH |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 2.7V~3.6V | |
| EEPROM | 32KB | |
| Program Storage Size | 1.5MB | |
| CPU Core | RXv2 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 120MHz | |
| Oscillator Type | Built-in |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- 32-bit RXv2 CPU core
- Max. operating frequency: 120 MHz
- Capable of 240 DMIPS in operation at 120 MHz
- Single precision 32-bit IEEE-754 floating point
- Two types of multiply-and-accumulation unit (between memories and between registers)
- 32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
- Divider (fastest instruction execution takes two CPU clock cycles)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions: Ultra-compact code
- Supports the memory protection unit (MPU)
- JTAG and FINE (one-line) debugging interfaces
- Low-power design and architecture
- Operation from a single 2.7- to 3.6-V supply
- Low power consumption: A product that supports all peripheral functions draws only 0.19 mA/MHz (Typ.)
- RTC is capable of operation from a dedicated power supply
- Four low-power modes
- On-chip code flash memory
- Supports versions with up to 2 Mbytes of ROM
- No wait cycles at up to 50 MHz or when the ROM cache is hit, one wait state at up to 100 MHz, two-wait state at above 100 MHz
- User code is programmable by on-board or off-board programming
- Programming/erasing as background operations (BGOs)
- A dual-bank structure allows exchanging the start-up bank
- On-chip data flash memory
- 32 Kbytes, reprogrammable up to 100,000 times
- Programming/erasing as background operations (BGOs)
- On-chip SRAM, no wait states
- 256K/640 Kbytes of SRAM (no wait states)
- 8 Kbytes of standby RAM (backup on deep software standby)
- Data transfer
- DMACAa: 8 channels
- DTCb: 1 channel
- EXDMAC: 2 channels
- DMAC for the Ethernet controller: 1 channel
- Reset and supply management
- Power-on reset (POR)
- Low voltage detection (LVD) with voltage settings
- Clock functions
- External crystal resonator or internal PLL for operation at 8 to 24 MHz
- Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz
- 120-kHz clock for the IWDTa
- Real-time clock
- Adjustment functions (30 seconds, leap year, and error)
- Real-time clock counting and binary counting modes are selectable
- Time capture function (for capturing times in response to event-signal input)
- Independent watchdog timer
- 120-kHz (1/2 LOCO frequency) clock operation
- Useful functions for IEC60730 compliance
- Oscillation-stoppage detection, frequency measurement, CRCA, IWDTa, self-diagnostic function for the A/D converter, etc.
- Register write protection function can protect values in important registers against overwriting
- Various communications interfaces
- Ethernet MAC (1 channel)
- PHY layer (1 channel) for host/function or OTG controller (1 channel) with full-speed USB 2.0 transfer
- CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 2 channels)
- SCIg and SCIh with multiple functionalities (up to 11 channels) Choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, simplified SPI, simplified I2C, and extended serial mode
- SCIi with 16-byte transmission and reception FIFOs (up to 2 channels)
- I2C bus interface for transfer at up to 1 Mbps (up to 3 channels)
- Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)
- Parallel data capture unit (PDC) for the CMOS camera interface
- Graphic-LCD controller (GLCDC)
- 2D drawing engine (DRW2D)
- SD host interface (optional: 1 channel) with a 1- or 4-bit SD bus for use with SD memory or SDIO
- SD slave interface (optional: 1 channel) with a 1- or 4-bit SD bus for use with SD host interface
- MMCIF with 1-, 4-, or 8-bit transfer bus width
- External address space
- Buses for full-speed data transfer (max. operating frequency of 60 MHz)
- 8 CS areas
- 8-, 16-, or 32-bit bus space is selectable per area
- Independent SDRAM area (128 Mbytes)
- Up to 25 extended-function timers
- 16-bit TPUa, MTU3a
- 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 channels)
- 12-bit A/D converter
- Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
- Self diagnosis, detection of analog input disconnection
- 12-bit D/A converter: 2 channels
- Temperature sensor for measuring temperature within the chip
- Encryption functions (optional)
- AES (key lengths: 128, 192, and 256 bits)
- Trusted Secure IP (TSIP)
- Up to 136 pins for general I/O ports
- 5-V tolerance, open drain, input pull-up, switchable driving ability
- Operating temp. range
- D-version: -40°C to +85°C
- G-version: -40°C to +105°C
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| Qty | Unit Price(Reference Only) | Total Amount |
|---|---|---|
| 1+ | $ 9.44 | $ 9.44 |
| 200+ | $ 3.6538 | $ 730.76 |
| 720+ | $ 3.5257 | $ 2538.50 |
| 1,440+ | $ 3.4625 | $ 4986.00 |
Standard Packaging720/Full Tray | ||
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Products Specifications
All
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | RENESAS | |
| Packaging | LFQFP-100(14x14) | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 12bit | |
| Number of I/O | 78 | |
| Operating Temperature | -40℃~+105℃ | |
| Program Memory Type | FLASH | |
| Voltage - Supply | 2.7V~3.6V | |
| EEPROM | 32KB | |
| Program Storage Size | 1.5MB | |
| CPU Core | RXv2 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 120MHz | |
| Oscillator Type | Built-in |
| Type | Description | |
|---|---|---|
| Category | Integrated Circuits (ICs)/Embedded/Microcontrollers | |
| Manufacturer | RENESAS | |
| Packaging | LFQFP-100(14x14) | |
| DAC (Bit) | 12bit | |
| ADC (Bit) | 12bit | |
| Number of I/O | 78 | |
| Operating Temperature | -40℃~+105℃ | |
| Program Memory Type | FLASH |
| Type | Description | |
|---|---|---|
| Voltage - Supply | 2.7V~3.6V | |
| EEPROM | 32KB | |
| Program Storage Size | 1.5MB | |
| CPU Core | RXv2 | |
| Core Size | 32 Bit | |
| CPU Maximum Speed | 120MHz | |
| Oscillator Type | Built-in |
Help & FeedbackShow similar products (0) >
Features
AI Translation
- 32-bit RXv2 CPU core
- Max. operating frequency: 120 MHz
- Capable of 240 DMIPS in operation at 120 MHz
- Single precision 32-bit IEEE-754 floating point
- Two types of multiply-and-accumulation unit (between memories and between registers)
- 32-bit multiplier (fastest instruction execution takes one CPU clock cycle)
- Divider (fastest instruction execution takes two CPU clock cycles)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions: Ultra-compact code
- Supports the memory protection unit (MPU)
- JTAG and FINE (one-line) debugging interfaces
- Low-power design and architecture
- Operation from a single 2.7- to 3.6-V supply
- Low power consumption: A product that supports all peripheral functions draws only 0.19 mA/MHz (Typ.)
- RTC is capable of operation from a dedicated power supply
- Four low-power modes
- On-chip code flash memory
- Supports versions with up to 2 Mbytes of ROM
- No wait cycles at up to 50 MHz or when the ROM cache is hit, one wait state at up to 100 MHz, two-wait state at above 100 MHz
- User code is programmable by on-board or off-board programming
- Programming/erasing as background operations (BGOs)
- A dual-bank structure allows exchanging the start-up bank
- On-chip data flash memory
- 32 Kbytes, reprogrammable up to 100,000 times
- Programming/erasing as background operations (BGOs)
- On-chip SRAM, no wait states
- 256K/640 Kbytes of SRAM (no wait states)
- 8 Kbytes of standby RAM (backup on deep software standby)
- Data transfer
- DMACAa: 8 channels
- DTCb: 1 channel
- EXDMAC: 2 channels
- DMAC for the Ethernet controller: 1 channel
- Reset and supply management
- Power-on reset (POR)
- Low voltage detection (LVD) with voltage settings
- Clock functions
- External crystal resonator or internal PLL for operation at 8 to 24 MHz
- Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz
- 120-kHz clock for the IWDTa
- Real-time clock
- Adjustment functions (30 seconds, leap year, and error)
- Real-time clock counting and binary counting modes are selectable
- Time capture function (for capturing times in response to event-signal input)
- Independent watchdog timer
- 120-kHz (1/2 LOCO frequency) clock operation
- Useful functions for IEC60730 compliance
- Oscillation-stoppage detection, frequency measurement, CRCA, IWDTa, self-diagnostic function for the A/D converter, etc.
- Register write protection function can protect values in important registers against overwriting
- Various communications interfaces
- Ethernet MAC (1 channel)
- PHY layer (1 channel) for host/function or OTG controller (1 channel) with full-speed USB 2.0 transfer
- CAN (compliant with ISO11898-1), incorporating 32 mailboxes (up to 2 channels)
- SCIg and SCIh with multiple functionalities (up to 11 channels) Choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, simplified SPI, simplified I2C, and extended serial mode
- SCIi with 16-byte transmission and reception FIFOs (up to 2 channels)
- I2C bus interface for transfer at up to 1 Mbps (up to 3 channels)
- Four-wire QSPI (1 channel) in addition to RSPIc (3 channels)
- Parallel data capture unit (PDC) for the CMOS camera interface
- Graphic-LCD controller (GLCDC)
- 2D drawing engine (DRW2D)
- SD host interface (optional: 1 channel) with a 1- or 4-bit SD bus for use with SD memory or SDIO
- SD slave interface (optional: 1 channel) with a 1- or 4-bit SD bus for use with SD host interface
- MMCIF with 1-, 4-, or 8-bit transfer bus width
- External address space
- Buses for full-speed data transfer (max. operating frequency of 60 MHz)
- 8 CS areas
- 8-, 16-, or 32-bit bus space is selectable per area
- Independent SDRAM area (128 Mbytes)
- Up to 25 extended-function timers
- 16-bit TPUa, MTU3a
- 8-bit TMRa (4 channels), 16-bit CMT (4 channels), 32-bit CMTW (2 channels)
- 12-bit A/D converter
- Two 12-bit units (8 channels for unit 0; 21 channels for unit 1)
- Self diagnosis, detection of analog input disconnection
- 12-bit D/A converter: 2 channels
- Temperature sensor for measuring temperature within the chip
- Encryption functions (optional)
- AES (key lengths: 128, 192, and 256 bits)
- Trusted Secure IP (TSIP)
- Up to 136 pins for general I/O ports
- 5-V tolerance, open drain, input pull-up, switchable driving ability
- Operating temp. range
- D-version: -40°C to +85°C
- G-version: -40°C to +105°C
C3207944 EasyEDA Library
Compliance & Export Codes
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991a2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC | |
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS |
| Type | Details |
|---|---|
| RoHS | ROHS3 Compliant |
| ECCN | 3A991a2 |
| CNHTS | 8542319090 |
| USHTS | |
| TARIC |
| Type | Details |
|---|---|
| CAHTS | |
| BRHTS | |
| INHTS | |
| MXHTS | |
Alternative Parts
| MPN | Manufacturer | Packaging | Availability | Unit Price | ||
|---|---|---|---|---|---|---|
| R5F5651CDDFP#30 | RENESAS | LFQFP-100(14x14) | 53 | $ 16.4412 | ||
| R5F5651EHDFP#10 | RENESAS | LQFP-100(14x14) | 7 | $ 10.9925 | ||
| R5F5651CDDFP#10 | RENESAS | LQFP-100(14x14) | 5 | $ 11.6918 | ||
| R5F565NCDDFP#30 | RENESAS | LFQFP-100(14x14) | 3 | $ 9.7309 | ||
| R5F565NEDDFP#30 | RENESAS | LFQFP-100(14x14) | 2 | $ 11.0624 | ||
| R5F5651CHGFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 9.44 | ||
| R5F565NCHGFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 9.9568 | ||
| R5F5651CDGFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 9.5449 | ||
| R5F565NEDGFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 9.9568 | ||
| R5F5651EDGFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 9.44 | ||
| R5F5651EHGFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 9.9568 | ||
| R5F565NEHGFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 10.4537 | ||
| R5F565NCDDFP#10 | RENESAS | LQFP-100(14x14) | 0 | $ 8.628 | ||
| R5F565NCHDFP#30 | RENESAS | LFQFP-100(14x14) | 0 | $ 16.9535 | ||
| R5F565NEDDFP#10 | RENESAS | LQFP-100(14x14) | 0 | $ 8.892 | ||
| R5F5651EDDFP#10 | RENESAS | LFQFP-100(14x14) | 0 | $ 9.0172 | ||
| R5F5651EDDFP#30 | RENESAS | LFQFP-100(14x14) | 0 | $ 16.0869 | ||
| R5F564MFCDFP#31 | RENESAS | LFQFP-100(14x14) | 0 | $ 13.606 | ||
| R5F564MLDDFP#31 | RENESAS | LFQFP-100(14x14) | 0 | $ 32.7362 | ||
| R5F564MFDDFP#11 | RENESAS | LFQFP-100(14x14) | 0 | $ 13.7911 |